<Error Message>
Loading dcfifo_test.dcfifo_test_xxxxx
Error (suppressible): (vsim-10000) C:/<path>/sim/dcfifo_test.dcfifo_test_xxxxx.v( xx): Unresolved defparam reference to 'dcfifo_component' in dcfifo_component.enable_ecc.
Time: 0 ps Iteration: 0 Instance: /tb/dcfifo_test. dcfifo_test_xxxxx_component/fifo_0 File: C:/<path>/sim/dcfifo_test.dcfifo_test_xxxxx.v
It seems to be caused by the VHDL library being specified at vsim runtime.
Please delete -L altera_mf and specify -L altera_mf_ver to run (load) the simulation.
For Nativelink, please run the
vsim command with -L altera_mf deleted.
Alternatively, you can set output netlist in Settings > Simulation to Verilog.
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Category: Simulation
Tools: ModelSim®-Intel® FPGA Edition
Devices: -