Is it safe to gate pll_ref_clk at startup on Stratix® 10? Also, how do I perform a recalibration?

pll_ref_clk cannot be gated. It should be directly connected to the input pin.
To execute recalibration, perform local_reset_req under the following conditions.

(1) local_reset_done =1
(2) High width must be more than 2clk width of core_clk.

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Category: External Memory Interface
Tools: -
Device: ^Stratix® 10