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I have a PCI-Express (PCIe) implementation on an Arria® V GX. When I compile with the transceiver pins assigned, an error occurs in the Fitter.

I have a PCI-Express (PCIe) implementation on an Arria® V GX. When I compile with the transceiver pins assigned, an error occurs in the Fitter.

  • Updated

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Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 Receiver channel(s))
Error (175020 ): Illegal constraint of Receiver channel that is part of xxx to the region (x, y) to (x, y): no valid locations in region

The PCIe Hard IP Block has a fixed location on the device, with fixed TX/RX and Reset pins.
(If multiple Hard IP Blocks exist, you can select which Hard IP Block to use.)
Once compiled without pin assignment, Quartus® Prime will automatically assign the most appropriate pins.
Refclk can be reassigned within the Dedicated pins.

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Category: PCI-Express
Tool: Quartus® Prime
Device: Arria® V

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