The Arria® 10 SoC supports five types of Ethernet MAC interfaces (MII, GMII, RMII, RGMII, and SGMII) that utilize FPGA-side I/O.
However, when selecting FPGA Routing on the Platform Designer, only GMII/MII can be selected.
Except for GMII/MII, all of them require adapter logic to be implemented on the FPGA side.
In particular, for RMII, adapter logic is not provided, so you need to create your own adapter logic.
Please refer to the following document for details.
Arria 10 Hard Processor System Technical Reference Manual" (683711 | 2026.01.16)
https://docs.altera.com/r/docs/683711/25.3.1/arria-10-hard-processor-system-technical-reference-manual/phy-interface
(Item 18.1.5 PHY Interface 14)
The following description is applicable to interfaces that require adaptor logic, as indicated by "∗with additional required adaptor logic∗".
The PHY interfaces supported using the HPS I/O pins are:
- Reduced Media Independent Interface (RMII)
- Reduced Gigabit Media Independent Interface (RGMII)
The PHY interfaces supported using the FPGA I/O pins are:
- Media Independent Interface (MII)
- Gigabit Media Independent Interface (GMII)
- Reduced Media Independent Interface (RMII) with additional required adaptor logic
Note: Additional adaptor logic for RMII not provided.
- Reduced Gigabit Media Independent Interface (RGMII) with additional required adaptor logic
- Serial Gigabit Media Independent Interface (SGMII) supported through transceiver I/O or high-speed low-voltage differential signaling (LVDS) with soft clock data recover (CDR) I/O with additional required adaptor logic
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Category: SoC
Tools: Quartus® Prime (Platform Designer)
Device: Arria® 10