Regarding the MMU settings for the Cyclone® V SoC (Cortex-A9), what does Inner / Outer mean, which can be selected as the Cache attribute setting?

Each of them is as follows

inner cacheability attribute ... L1 cacheability attribute
・outer cacheability attribute ... L2 cacheability attribute

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Category: SoC
Tool: Quartus® Prime
Device: Cyclone® V