For the two CAN controller systems (can0, can1) on the Hard Processor System (HPS) side,
each has two Message RAM Interface channels, allowing two ID settings per channel.
--------------------
Category: SoC
Tools: -
Device: Cyclone® V
For the two CAN controller systems (can0, can1) on the Hard Processor System (HPS) side,
each has two Message RAM Interface channels, allowing two ID settings per channel.
--------------------
Category: SoC
Tools: -
Device: Cyclone® V