Please refer to the following user guide for the simulation procedure.
(Reference)
Arria 10 and Cyclone 10 GX Avalon Memory-Mapped (Avalon-MM) Interface for PCI Express User Guide
(14. Avalon-MM Testbench and Design Example for Root Port)
The key point in the procedure is to enable BAR0 (64-bit) or BAR0 & 1 (32-bit) in the Base Address Registers tab of IP Settings.
Otherwise, the TXS and CRA ports of the generated simulation model will be unconnected and the simulation will not proceed correctly.
(Excerpt from Example Design Generation, 14.1.1.)
In the Base Address Registers tab, only enable BAR0, or BAR0 and BAR1. All other BARs are disabled in the current Root Port design example.
If you set BAR0 to use 64-bit prefetchable memory, you need to disable BAR1.
If you set BAR0 to use 32-bit prefetchable memory or 32 -bit non-prefetchable memory, you can enable or disable BAR1
Now, follow the steps in 14.2.1, "Simulating the Design Example" with the generated model.
We have verified that the simulation runs successfully with the following simulators
- ModelSim® SE-64 2019.1
- ModelSim®-Intel® FPGA Edition 10.6d (including Starter Edition)
(Supplemental)
Please perform this in a Linux environment, as it may not complete successfully in a Windows OS environment due to file path length limitations.
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Category: PCI-Express
Tools: Quartus® Prime / ModelSim®
Device: Arria® 10