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I am evaluating OpenCL™ on an Stratix® 10 evaluation kit. When I set it to PCI-Express 16 lanes and check with "aocl diagnose", I get the message "PCIe dev_id = 5170, bus:slot.func = 01:00.00, Gen3 x8" which is 8 lanes.

I am evaluating OpenCL™ on an Stratix® 10 evaluation kit. When I set it to PCI-Express 16 lanes and check with "aocl diagnose", I get the message "PCIe dev_id = 5170, bus:slot.func = 01:00.00, Gen3 x8" which is 8 lanes.

  • Updated

Please use x8 because OpenCL™ BSP supports only up to x8.

(Reference) Can Stratix® 10 GX FPGA Development Kit support PCIe gen3x16 for OpenCL? 
https://community.altera.com/kb/knowledge-base/can-intel%C2%AE-stratix%C2%AE-10-gx-fpga-development-kit-support-pcie-gen3x16-for-opencl%E2%84%A2/344307

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Category: OpenCL™ 
Tools: Intel® FPGA SDK for OpenCL™ 
Device: Stratix® 10

 

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