On an Arria® V SoC, I am trying to route an HPS SPI master device to an FPGA, but there is no sclk.

When the pins of the SPI master device (spim) implemented in the Hard Processor System (HPS) are routed to the FPGA side, 
sclk appears as a separate port.

The spim_sclk_out port may not appear due to the filter function in Platform Designer. 
(For example, if the Hide Clocks and Resets filter is selected, it will not be displayed.) 
In this case, try All Interfaces as the Filter type.

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Category: SoC 
Tool: Quartus® Prime 
Device: Arria® V