When used in DPA mode, no timing constraints are required for the target I/O.
Please refer to the following document.
(Reference) LVDS SERDES FPGA IP User Guide: Arria 10 and Intel Cyclone 10 GX Devices
https://malt.zendesk.com/hc/en-us/articles/900006261083-When-using-LVDS-Rx-IP-in-DPA-mode-with-Arria-10-is-it-necessary-to-calculate-RSKM-etc-and-add-SDC-constraints
(I/O Timing Analysis section)
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Category: IP (Other)
Tools: Quartus® Prime
Devices: Arria® 10 FPGA