When performing an Arria® 10 I/O PLL Reconfiguration, a register is set for the PLL Reconfig Intel FPGA IP, but the value written to the register is not written correctly. Why is this?

PLL Reconfig Intel FPGA IP's register access clock must be supplied by an external stable clock (free runnning clock) using mgmt_clk. 
Please refer to the following document for details.

AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria 10 and Cyclone 10 GX Devices
Design Considerations • AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria 10 and Cyclone 10 GX Devices • Altera Documentation and Resources Center
(Design Considerations > Other Design Considerations) 
(excerpt) 
I/O PLL reconfiguration interface supports a free running mgmt_clk signal.

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Category: Configuration/Programming 
Tools:- 
Device: Arria® 10