Skip to main content

A proven design with an RTL simulation of an ADC in a MAX® 10 FPGA in ModelSim* , ported to another directory and performing the same task, results in an error message.

A proven design with an RTL simulation of an ADC in a MAX® 10 FPGA in ModelSim* , ported to another directory and performing the same task, results in an error message.

  • Updated

＜Error Message

 Protected: /( Path Name )/adcblock_instance/primitive_instance/inst/inst/<protected>/<protected 
** Error (suppressible): (vsim-PLI-3084) nofile(38): $fscanf : Argument 1 is not a valid file descriptor.

 

This error occurs when a project is ported without changing the path to the file containing the simulation data set in the Modular ADC IP core.

For the ported project, start the IP Parameter Editor and check the User created expected output file field of the Modular ADC IP. 
If the path before porting remains, specify the data file in the path after porting again.

If the path is changed, "Regenerate" is required.

-------------------- 
Category: IP (Other)/ Simulation 
Tool: ModelSim* 
Device: MAX® 10

 

Related articles