Datarate : 5000Mbps, FPGA fabric : 10bit, error due to "Parallel clock frequency = 500MHz > Datasheet tolerance".
The parallel clock of Transceiver -> FPGA Fabric has the following frequency limitation:
Cyclone V Device Datasheet
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices • Cyclone V Device Datasheet • Altera Documentation and Resources Center
Table 26. Transceiver-FPGA Fabric Interface Specifications for Cyclone V GX, GT, SX, and ST Devices
The specific parallel clock frequency should be calculated as A divided by B.
(A) Data rate
(B) FPGA fabric / Standard TX,RX PCS interface width
Errors can be avoided by increasing the bandwidth of the FPGA Fabric.
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Category: Transceivers
Tool: Quartus® Prime
Device: Cyclone® V