Are there any regulations in controlling HPS_nPOR and HPS_nRST of the Arria® 10 SoC?

The following regulations must be observed

　HPS cold reset pulse width 600ns(Min) 
HPS warm reset pulse width 600ns(Min)

(Reference) 
https://docs.altera.com/r/docs/683771/current/arria-10-device-datasheet/hps-specifications

Table 57. HPS Reset Input Requirements for Intel Arria 10 Devices 
(search for OCT Calibration Block Specifications)

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Category: SoC 
Tools: SoC EDS 
Devices: Arria® 10