1. Overview (Configuration diagram including IPs)
This content describes how to configure the minimum required IP parameters, set up the BSP Editor, and generate the necessary files to boot the Nios® II Processor from a Configuration ROM (or a third-party Configuration ROM) using either Boot Copier or XIP.
Please refer to the following contents for the difference between XIP and Boot Copier.
・Configuration of Nios® II Boot and settings for each Boot Option
If you want to boot from Quad SPI Flash (QSPI Flash) connected to User I/O pins, please refer to the following contents.
・Nios® II Boot Option ~ QSPI Flash ~ (using User I/O IF)
Please refer to the following contents for the Boot method using Generic Serial Flash Interface Intel® FPGA IP.
・Nios® II Boot Option ~ Boot method using Generic Serial Flash Interface ~ - (In Japanese)
The minimum IP requirements are as follows (Intel® Quartus® Prime development software ver 18.1).
- Nios® II Processor
- On-Chip Memory (RAM or ROM) Intel® FPGA IP: Execution Memory
- Serial Flash Controller Intel® FPGA IP: Boot memory (EPCQ Flash) Controller
Figure 1 shows the Platform Designer configuration.
[Figure 1] Platform Designer configuration example
The following sections describe the settings of various parameters.
1-1. Nios® II Processor
Set Reset Vector / Exception Vector.
The setting differs depending on whether the XIP or Boot Copier method is used. Please refer to the following.
"2. Nios® II settings for execution from EPCQ with XIP"
"3. Nios® II settings for execution from EPCQ with Boot Copier"
1-2. On-Chip Memory (RAM or ROM) Intel® FPGA IP
Set the Total Memory Size required for software execution as shown in Figure 2.
[Figure 2] On-Chip Memory parameter setting example
1-3. Serial Flash Controller Intel® FPGA IP
Select x1 (Standard) or x4 (Quad) for the Configuration Device* and I/O mode to be used.
[Figure 3] Serial Flash Controller parameter setting example
The Serial Flash Controller has an upper input clock limit of 25MHz.
*When using a third-party Configuration ROM (e.g. MT25Q), it will not appear in
Configuration Device, so the following Knowledge Database (KDB) support is required.
<KDB>.
How do I enable Micron's MT25Q device support in replacement to End Of Life (EOL) EPCQ(>=256Mb) and EPCQ-L devices?
For more information on other Flash Controllers, please refer to this content.
・Embedded Peripherals IP - Comparison of various Flash Controllers - (In Japanese)
1-4. Quartus® Prime settings
Serial Flash Controller parameter settings must be configured as shown in Figure 4 as a Quartus® Prime restriction.
Open Assignment tab > Device > Device and Pin Options > Configuration.
- Configuration scheme: Set the I /O mode set in the Serial Flash Controller parameter
- Active serial clock source: Set the clock frequency when configuring the FPGA
[Figure 4] Device and Pin Options in Quartus® Prime
2. Nios® II settings for execution from EPCQ with XIP
Explains the Reset Vector / Exception Vector settings and BSP Editor settings for the Nios® II Processor.
The Boot method of the XIP is to use the Nios® II Processor on the EPCQ Flash. It is an effective configuration for systems that do not have enough On-Chip RAM. .rodata, .rwdata, .exceptions, etc. are copied onto RAM using the alt_load() function. The main software, .text, remains on the EPCQ Flash and Nios® II is executed on the EPCQ Flash.
Hardware breakpoints are required to debug XIP configurations, and the method is introduced in the following contents.
・How to use Run/Debug Configuration settings in Nios® II SBT for Eclipse - (In Japanese)
2-1. Parameter settings for Nios® II Processor in XIP configuration
When booting Nios® II with XIP, there are two Vector settings for the Nios® II Processor.
- Reset Vector / Exception Vector are both set to Serial Flash Controller.
- Set Serial Flash Controller for Reset Vector and On-Chip RAM or External RAM for Exception Vector.
[Figure 5] Nios® II Vector setting in XIP configuration
Setting RAM for the Exception Vector allows exception handling to run faster than with Flash, which can improve Nios® II performance.
< How to set Reset Vector offset >
The Programming File stored in EPCQ Flash consists of an SOF file and a HEX file, and the Serial Flash Controller can freely set the address value of the HEX file.
Therefore, it is necessary to know the end address of the SOF file and set the start address value of the HEX file to Reset Vector Offset.
Compile Quartus® Prime onece to generate the SOF file.
It is possible to calculate the end address of the SOF file from the size of the SOF file, but if you convert only the corresponding SOF file to a JIC file by Convert Programming Files, you can accurately grasp the end address from the address values of the SOF file described in the MAP file generated together with it.
Set the Reset Vector Offset to the address value that is slightly removed from the end address in the SOF file.
(In the example in Figure 6, Reset Vector Offset is set to 0x420000 for the SOF file end address: 0x41F013.)
[Figure 6] How to set Reset Vector offset
The Boot Copier is not necessary because the alt_load() function is used to copy the Exception Vector from the EPCQ Flash to the On-Chip RAM or external RAM.
Once the Reset Vector Offset setting has been completed and the design has been created, Quartus® Prime is compiled and SOF file is generated.
2-2. BSP Editor settings for Nios® II SBT in XIP configuration
Start the Nios® II SBT and generate Application and BSP.
Start BSP Editor and set Linker Script and alt_load() function options.
Set the Linker Script as shown in Figure 7.
Set the .text section to Serial Flash Controller, and set other sections to On-Chip RAM or external RAM.
[Figure 7] Linker Script settings in XIP configuration
In the Main tab, under Settings > Advanced > hal > linker, set the alt_load() function options as shown in Figure 8.
The setting items differ depending on the two types of Nios® II Processor Vectors settings described above.
[Figure 8] alt_load() function settings for XIP configuration
This completes the various settings to realize the XIP configuration.
The next step is to generate the HEX and Programming files for EPCQ Flash, see section 4.
"4. How to generate the Programming File"
3. Nios® II settings for execution from EPCQ with Boot Copier
Explains the Reset Vector / Exception Vector settings and BSP Editor settings for the Nios® II Processor.
3-1. Parameter settings for Nios® II Processor in Boot Copier configuration
When booting the Nios® II with Boot Copier, the Nios® II Processor has only one Vectors setting.
- Set the Reset Vector to Serial Flash Controller and the Exception Vector to On-Chip RAM or external RAM.
[Figure 9] Nios® II Vector setting in Boot Copier configuration
< How to set Reset Vector offset >
The Programming File stored in EPCQ Flash consists of an SOF file and a HEX file, and the Serial Flash Controller can freely set the address value of the HEX file.
Therefore, it is necessary to know the end address of the SOF file and set the start address value of the HEX file to Reset Vector Offset.
Compile Quartus® Prime onece to generate the SOF file.
It is possible to calculate the end address of the SOF file from the size of the SOF file, but if you convert only the corresponding SOF file to a JIC file by Convert Programming Files, you can accurately grasp the end address from the address values of the SOF file described in the MAP file generated together with it.
Set the Reset Vector Offset to the address value that is slightly removed from the end address in the SOF file.
(In the example in Figure 10, Reset Vector Offset is set to 0x420000 for the SOF file end address: 0x41F013.)
[Figure 10] How to Set Reset Vector offset
Once the Reset Vector Offset setting has been completed and the design has been created, Quartus® Prime is compiled and SOF file is generated.
3-2. BSP Editor settings for Nios® II SBT in Boot Copier configuration
Start the Nios® II SBT and generate Application and BSP.
Start BSP Editor and set Linker Script and alt_load() function options.
Set the Linker Script as shown in Figure 11.
Set the .text section to On-Chip RAM or external RAM, and set other sections to On-Chip RAM or external RAM.
[Figure 11] Linker Script settings in Boot Copier configuration
Then, set the alt_load() function options in the Settings > Advanced > hal > linker item in the Main tab as shown in Figure 12.
The Boot Copier configuration does not use alt_load(), so remove all check boxes.
[Figure 12] alt_load() function settings for Boot Copier configuration
This completes the various settings to realize the Boot Copier configuration.
After writing the SOF file to the FPGA and verifying that the software works correctly with the "Run As" of the Nios® II SBT, the next step is to generate the HEX file and Programming file to be stored in the EPCQ Flash, see section 4.
"4. How to generate the Programming File"
4. How to generate the Programming File
After the software has been compiled by Nios® II SBT and the ELF file has been generated, the next step is to generate the HEX file. You can have HEX files in EPCQ Flash by converting HEX files to JIC files along with SOF files.
4-1. Generating a HEX file
Once the ELF file has been generated, right-click on the Nios® II application as shown in Figure 13 and use Make Targets > Build... > mem_init_generate > Build to generate the HEX file.
[Figure 13] mem_init_generate for HEX
There are three main types of files generated by mem_init_generate.
- meminit.qip: Used by registering to the project when Booting from On Chip RAM
- on_chip_ram.hex: Used as the initial value file of RAM when booting from On Chip RAM
- <Flash_Controller_Name>.hex: Software file to be included in the JIC file
4-2. Generating the JIC File
Once the HEX file is generated, use Convert Programming Files to generate a JIC file containing the SOF and HEX files.
Launch Quartus® Prime > file tab > Convert Programming Files. Configure the settings as shown in Figure 14.
(1) Set Programming file type to JTAG Indirect Configuration File (.jic)
(2) Select the model number of the appropriate Configuration ROM for Configuration Device
(3) Set Mode to Active Serial or Active serial ×4
(4) Select target device for Flash loader
(5) Select SOF file for SOF Data
(6) Click "Add Hex Data" and select "Absolute addressing" or "Big endian"
(7) Register the appropriate software HEX file in HEX file and click OK
[Figure 14] Convert Programming Files at JIC generation
Generate a JIC file with Convert Programming Files, and actually program it into the Configuration ROM to check the operation.
Recommendation Page
We have prepared a "Nios® II Summary Page - (In Japanese)" that summarizes various information on Nios® II. Please refer to this page as well, as it is full of useful information other than this article.
- Nios® II Summary Page - (In Japanese)