1. Overview (Configuration diagram including IPs)
This content describes how to boot a Nios® II processor from Quad SPI Flash (QSPI Flash) connected to the User I/O pins via Boot Copier or XIP, including the minimum necessary IP parameters, BSP Editor settings, and the steps to generate various files.
Please refer to the following contents for the difference between XIP and Boot Copier.
・Configuration of Nios® II Boot and settings for each Boot Option
Please also refer to our website, where similar contents with sample designs are available.
If you want to boot from AS Interface Configuration ROM, please refer to the following contents.
・Nios® II Boot Option ~ EPCQ Flash ~ (using AS IF)
Please refer to the following contents for how to Boot using Generic Serial Flash Interface Intel® FPGA IP.
・Nios® II Boot Option ~ Boot Method using Generic Serial Flash Interface ~ - (In Japanese)
Two designs are required for this project.
-
Parallel Flash Loader design (PFL design)
Design to write Nios® II software program created with Nios® II SBT to QSPI Flash via PFL. -
Main design (design with Nios® II)
Design with Nios® II implemented to execute Nios® II software program stored in QSPI Flash
First, let's look at the IP used in each design.
1-1. Parallel Flash Loader Design (PFL Design)
The minimum IP requirements are the following IP (Intel® Quartus® Prime development software ver 18.1 as an example).
When configured with Quartus® Prime, PFL RTL Viewer is shown in Figure 1.
[Figure 1] PFL RTL Viewer example
1-1-1. Parallel Flash Loader Intel® FPGA IP
The parameter settings of Parallel Flash Loader Intel® FPGA IP should be configured as shown in Figure 2 and Figure 3 according to the environment in which it is used.
[Figure 2] PFL parameter setting example
[Figure 3] PFL parameter setting example
After designing the Parallel Flash Loader hierarchy and completing various constraints such as PIN assignment and timing constraints, compile and generate the SOF file.
1-2. Main design (design with Nios® II)
The minimum IP requirements are the following IPs (Intel® Quartus® Prime development software ver 18.1).
- Nios® II Processor
- On-Chip Memory (RAM or ROM) Intel® FPGA IP: Execution Memory
-
Generic QUAD SPI controller II Intel® FPGA IP: Boot memory (QSPI Flash) controller
Figure 4 shows the Platform Designer configuration.
[Figure 4] Platform Designer configuration example
1-2-1. Nios® II Processor
Set Reset Vector / Exception Vector.
The settings are different depending on whether XIP or Boot Copier is used.
"2. Nios® II settings for XIP from QSPI Flash"
"3. Nios® II settings for executing with Boot Copier from QSPI Flash"
1-2-2. On-Chip Memory (RAM or ROM) Intel® FPGA IP
Set the Total Memory Size required for software execution as shown in Figure 5.
[Figure 5] On-Chip Memory parameter setting Example
1-2-3. Generic QUAD SPI controller II Intel® FPGA IP
Select the QSPI Flash Device and I/O mode to be used as x4 (Quad).
[Figure 6] Generic QUAD SPI controller setting example
For other Flash Controllers, please refer to the following contents.
・Embedded Peripherals IP - Comparison of Various Flash Controllers - (In Japanese)
1-2-4. Quartus® Prime settings
For devices other than MAX® 10, the configuration method used must be set as shown in Figure 7 as a Quartus® Prime constraint. For MAX® 10 devices, the Configuration scheme is Internal Configuration.
Navigate to Assignment tab -> Device -> Device and Pin Options -> Configuration.
- Configuration scheme: Set the format of the Configuration according to the configuration you are using.
- Active serial clock source: Set the clock frequency when configuring the FPGA.
[Figure 7] Device and Pin Options in Quartus® Prime
2. Nios® II settings for XIP from QSPI Flash
Explains the Reset Vector / Exception Vector settings and BSP Editor settings for the Nios® II Processor.
Since the XIP Boot method runs Nios® II Processor on QSPI Flash, it is an effective configuration for systems that do not have enough On-Chip RAM.
.rodata, .rwdata, .exceptions, etc. are copied onto RAM using the alt_load() function. The main software, .text, remains on the QSPI Flash and Nios® II is executed on the QPIS Flash.
Hardware breakpoints are required to debug the XIP configuration, and the method is introduced in the following contents.
・How to use Run/Debug Configuration settings in Nios® II SBT for Eclipse - (In Japanese)
2-1. Parameter settings for Nios® II Processor in XIP configuration
When booting Nios® II with XIP, there are two types of Vectors settings for the Nios® II Processor.
- Set Generic QUAD SPI Controller with Reset Vector and Exception Vector
- Set Reset Vector to Generic QUAD SPI Controller, and set Exception Vector to On-Chip RAM or External RAM
[Figure 8] Nios® II Vector settings in XIP configuration
Setting RAM in the Exception Vector allows exception handling to run faster than in Flash, and improves Nios® II performance.
Now that you have configured Platform Designer, run "Generate" and compile on Quartus® Prime to generate SOF file.
2-2. BSP Editor settings for Nios® II SBT in XIP configuration
Start the Nios® II SBT and generate Application and BSP.
Start BSP Editor and set Linker Script and alt_load() function options.
Set the Linker Script as shown in Figure 9.
Set the .text section to Generic QUAD SPI Controller, and set other sections to On-Chip RAM or external RAM.
[Figure 9] Linker Script settings in XIP configuration
In the Main tab, under Settings -> Advanced -> hal -> linker, set the alt_load() function options as shown in Figure 10.
The setting items differ depending on the two types of Nios® II Processor Vectors settings described above.
[Figure 10] alt_load() function settings for XIP configuration
This completes the various settings to realize the XIP configuration.
The next step is to generate the HEX and Programming files for QSPI Flash, see section 4.
"4. How to generate and write the Programming File"
3. Nios® II settings for executing with Boot Copier from QSPI Flash
Explains the Reset Vector / Exception Vector settings and BSP Editor settings for the Nios® II Processor.
3-1. Nios® II Processor parameter settings in Boot Copier configuration
When booting the Nios® II with Boot Copier, the Nios® II Processor has only one Vectors setting.
- Set Reset Vector to Generic QUAD SPI Controller and set Exception Vector to On-Chip RAM or External RAM
[Figure 11] Nios® II Vectors settings in Boot Copier configuration
Now that you have configured Platform Designer, run "Generate" and compile on Quartus® Prime to generate SOF file.
3-2. BSP Editor settings for Nios® II SBT in Boot Copier configuration
Start the Nios® II SBT and generate Application and BSP.
Start BSP Editor and set Linker Script and alt_load() function options.
Set the Linker Script as shown in Figure 12.
Set the .text section to On-Chip RAM or external RAM, and set other sections to On-Chip RAM or external RAM.
[Figure 12] Linker Script settings in Boot Copier configuration
In the Main tab, under Settings -> Advanced -> hal -> linker, set the alt_load() function options as shown in Figure 13.
Since the Boot Copier configuration does not use alt_load(), remove all check boxes.
[Figure 13] alt_load() function settings for Boot Copier configuration
This completes the various settings to realize the Boot Copier configuration.
After writing the SOF file to the FPGA and verifying that the software works correctly with the "Run As" of the Nios® II SBT, the next step is to generate the HEX file and Programming file to be stored in the QSPI Flash, see section 4.
"4. How to generate and write the Programming File"
4. How to generate and write the Programming File
After completing the various settings for the main design, generate the Platform Designer, and fully compile Quartus® Prime to generate the SOF. After software development with Nios® II SBT, run Build to generate the ELF file.
4-1. HEX File generation
Once the ELF file has been generated, right-click on the Nios® II application as shown in Figure 14 and use Make Targets > Build... > mem_init_generate > Build to generate the HEX file.
[Figure 14] mem_init_generate for HEX
There are three main types of files generated by mem_init_generate.
- meminit.qip: Used by registering to the project when Booting from On Chip RAM
- on_chip_ram.hex: Used as the initial value file of RAM when booting from On Chip RAM
- <generic_quad_spi_controller>.hex: [this time] Software file to be stored in QSPI Flash
4-2. Generation of POF file
Generate POF file containing the SOF file of main design and another POF file containing the Nios® II software file.
As shown in Figure 15, use Convert Programming Files to generate a POF file containing the SOF file for the main design.
*MAX® 10 for devices other than FPGAs, a JIC file can be written to the Configuration ROM instead of a POF file.
・Programming to the EPCQ device via FPGA (JIC programming) - (In Japanese)
[Figure 15] Generating POF File for Hardware
Generate a POF file containing the HEX file of the Nios® II software file with Convert Programming Files as shown in Figure 16.
At this time, set the Bit-Level endianness setting to Big Endian.
Reference Content: Intel: MAX® 10 cannot be booted from external Flash memory (QSPI).
The following User Guide describes the procedure for Passive Serial Configuration (Supported Configuration Modes for Non-FPGA MAX® 10 Devices), but it can be used for QSPI Flash wthich is not Configuration ROM by registering only HEX as shown in Figure 16.
・Parallel Flash Loader Intel® FPGA IP User Guide >1.4.1. Converting .sof Files to a .pof
[Figure 16] Generating POF File for Software
4-3. Writing POF Files
1) Write the SOF file of the Parallel Flash Loader design into the FPGA.
2) In this state, press Auto Detect to recognize the QSPI Flash (see Figure 17).
3) Register the software POF file generated in Figure 16 in the item where Device is QSPI Flash (for reference: Figure 17)
4) Press Start, and when the writing is finished, the writing to QSPI Flash is complete (for reference: Figure 17)
5) Write the POF file for hardware into CFM (Configuration ROM except MAX® 10)
6) Power on the FPGA again, and then verify that Configuration and Nios® II boot up.
If you do not boot, review the Bit-Level endianness setting when generating the software POF file.
[Figure 17] Writing to QSPI Flash
Recommendations
We have prepared a "Nios® II Summary Page - (In Japanese)" that summarizes various information on Nios® II. Please refer to this page as well, as it is full of useful information other than this article.
- Nios® II Summary Page - (In Japanese)