1. Introduction
We are often asked by customers using Intel® SoC FPGAs to issue a reset to the FPGA from the Hard Processor System (HPS).
This document introduces the means to issue a reset from the HPS to the FPGA.
2. Ports where resets are output
The ports on which resets are output are h2f_reset or h2f_cold_reset.
For details, see the screen capture of the Platform Designer (formerly Qsys) in Figure 1 below.
As explained in section "3. Registers for issuing reset" you can select either h2f_reset or h2f_cold_reset for the reset depending on the register to be controlled.
[Figure 1] Reset Port
No configuration is required to create a port for h2f_reset, but a separate configuration is required to use a port for h2f_cold_reset.
To create the h2f_cold_reset port, go to the Platform Designer and check the Enable HPS-to-FPGA cold reset output checkbox in the Resets category under the FPGA Interfaces tab in the HPS parameters as shown in Figure 2 below.
[Figure 2] Enable h2f_cold_reset setting
Arria® 10 also has the same settings as in Figure 2, but the reset control method is different.
Reference: Please refer to the following document for details.
How to issue a reset signal from the HPS to the FPGA (Arria® 10)
3. Registers for issuing reset
The HPS Reset Manager has a MISCMODRST register, which can output a reset signal by controlling this register.
To issue a reset signal to h2f_reset, set 1 to s2f (6th bit) of MISCMODRST.
To issue a reset signal to h2f_cold_reset, set 1 to s2fcold (7th bit) of MISCMODRST.
The register address of MISCMODRST is 0xFFD05020, so the access method is as follows.
- To issue to h2f_reset: Write 0x00000040 to 0xFFD05020
- To issue to h2f_cold_reset: Write 0x00000080 to 0xFFD05020
Reference: Please refer to the following document for register details.
Cyclone V HPS memory Map ⇒ Reset Manager Module Address Map ⇒ miscmodrst
Note that a reset can be issued by manipulating this register regardless of whether the FPGA and HPS are bridged or not.
Note:
The bridge between the FPGA and the HPS must be closed before issuing a reset.
The command to close the bridge between the HPS and FPGA is as follows.
$ run bridge_disable
4. Waveforms during reset
The waveform of the HPS reset port (h2f_reset / h2f_cold_reset) when the command "3. Registers for issuing reset" is executed was confirmed by Signal Tap.
●Waveform before issuing a reset :
Since h2f_reset / h2f_cold_reset is Low Active, the port names are h2f_cold_rst_n / h2f_rst_n as shown in Figure 3 below.
The waveform before reset is High because it is Low Active.
[Figure 3] h2f_reset / h2f_cold_reset before reset
●Waveform when a reset is applied to h2f_reset :
When "Write 0x00000040 to 0xFFD05020" is executed as described in "3. Registers for issuing reset", the signal of h2f_rst_n becomes Low as shown in Figure 4 below and reset is enabled.
[Figure 4] Waveform when reset is applied to h2f_reset
●Waveform when a reset is applied to h2f_cold_reset :
When "Write 0x00000080 to 0xFFD05020" is executed as described in "3. Registers for issuing reset", the signal of h2f_cold_reset_n becomes Low as shown in Figure 5 below and reset is enabled.
[Figure 5] Waveform when reset is applied to h2f_cold_reset