1. Introduction
We are often asked by customers using Intel® SoC FPGAs to issue a reset to the FPGA from the Hard Processor System (hereafter referred to as "HPS").
This document describes how to issue a reset from the HPS to the FPGA in Arria® 10.
2. How to issue a reset in the case of Arria® 10
In the case of Arria® 10, it is not possible to issue a reset to the FPGA without resetting the HPS due to register control.
Therefore, a reset is issued using GPIOs from the HPS to the FPGA.
Figure 1 below shows an image of this.
[Figure 1] Configuration to reset from HPS to FPGA (Arria® 10)
In the case of Arria® 10, GPIOs are used as resets, but in the case of Cyclone® V / Arria® V, resets can be issued to the FPGA without applying resets to the HPS by controlling the registers.
Reference: Please refer to the following document for details.
How to issuing a reset signal from the HPS to the FPGA (Cyclone® V / Arria® V)
3. Setting to enable GPIO from HPS to FPGA
To enable GPIO, check the Enable general purpose signals checkbox under the General category in the FPGA Interfaces tab of the HPS parameters in Platform Designer as shown in Figure 2 below.
[Figure 2] Setting to enable GPIO
When the above settings are enabled, the HPS will create a GPIO named h2f_gp as shown in Figure 3 below.
[Figure 3] GPIO Port
This h2f_gp is used to reset the FPGA.
The h2f_gp is generated in 32-bit width, and the FPGA Manager of the HPS controls which bit is toggled.
4. Registers to control h2f_gp
The FPGA Manager of HPS has a gpo register, which can be used to toggle h2f_gp by controlling this register.
Reference: Please refer to the following document for details.
Arria 10 HPS Register Map ⇒ fpga_mgr_fpgamgrregs Address Map ⇒ gpo
※Here is an excerpt of the gpo register (Figure 4)
[Figure 4] gpo register
Which bit of the 32-bit wide h2f_gp is controlled corresponds to the 32-bit configuration of the gpo register.
If you want to toggle bit 0 of h2f_gp, control bit 0 of the gpo register.
5. Waveform when controlling h2f_gp
This section explains how the GPIO port (h2f_gp) of the HPS changes when the command described in "4. Registers to control h2f_gp" is executed, based on the signal tap waveform.
- Waveform when bit 0 of h2f_gp is changed from Low to High :
As explained in "4. Register to control h2f_gp",
"Write 0x00000001 to 0xFFD03010"
When "Write 0x00000001 to 0xFFD03010" is executed, the h2f_gp signal changes from 0x00000000 to 0x00000001, as shown in Figure 5 below.
[Figure 5] Waveform when h2f_gp is changed from Low to High
- Waveform when bit 0 of h2f_gp is changed from High to Low :
As explained in "4. Register to control h2f_gp",
"Write 0x00000000 to 0xFFD03010"
When "Write 0x00000000 to 0xFFD03010" is executed, the h2f_gp signal changes from 0x00000001 to 0x00000000, as shown in Figure 6 below.
[Figure 6] Waveform when h2f_gp is changed from High to Low
6. Conclusion
In the case of Arria® 10, the GPIO between the HPS and the FPGA is used as a reset. The GPIO can be controlled by the gpo register in the FPGA Manager.
Reference: Please refer to the following document for register details.
Arria 10 HPS Register Map ⇒ fpga_mgr_fpgamgrregs Address Map ⇒ gpo