I have added the IP generated by the Intel® HLS compiler to the Platform Designer system and generated a simulation model (VHDL). When I simulate in ModelSim, the IP outputs indeterminate values.

Tool used: ^Quartus® Prime Standard Edition v17.1
^{ModelSim®-SE}

When the simulation model is set to VHDL during Generate in Platform Designer, the module names of the components generated by HLS in the automatically generated Platform Designer simulation top hierarchy (in the simulation folder) are incorrect and are not connected. The connection has not been made.

This can be avoided by either of the following methods.

(1) Correct the simulation top hierarchy module
component is <component name>_<component name>_internal, correct it to <component name>_internal.

(2) Generate simulation model in Verilog
Generate in Verilog, no problem

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Category: HLS
Tool: Quartus® Prime / Intel® HLS Compiler
Device: Cyclone® V