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I am implementing PCI-Express Avalon-ST IP on an Arria® 10 GX FPGA and I cannot find the Byte Enable signal that was available on the previous device.

I am implementing PCI-Express Avalon-ST IP on an Arria® 10 GX FPGA and I cannot find the Byte Enable signal that was available on the previous device.

  • Updated

The Byte Enable (rx_st_be) signal is not available on Arria® 10 FPGA.

(Reference) Arria 10 and Cyclone 10 GX Avalon Streaming Interface for PCI Express User Guide
https://docs.altera.com/r/docs/683647/18.0/arria-10-and-cyclone-10-gx-avalon-streaming-interface-for-pci-express-user-guide/document-revision-history
(see Document Revision History section)

2015.11.02 15.1 Made the following changes: 
Removed signal definition for rx_st_be. 
This signal is not supported for Arria® 10 devices.

Please design to implement the decision in the Last BE and First BE in the TLP.

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Category: PCI-Express 
Tools: Quartus® Prime 
Device: Arria® 10 FPGA

 

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