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Compiling qts_pam4_com from the Example Design included in the installer for the Intel® Stratix® 10 TX FPGA Signal Integrity Development Kit causes errors in logic synthesis.

Compiling qts_pam4_com from the Example Design included in the installer for the Intel® Stratix® 10 TX FPGA Signal Integrity Development Kit causes errors in logic synthesis.

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<Example Design>
stratix10TX_1st280yf55_si_revB_v18.1.2b277_v1.0\examples\qts_pam4_com\qts_pam4_com\pam4_xcvr_com.qpf

<Example error message>
Error (13305): Verilog HDL error at pam4_xcvr_com.v(130): can't find port "rsfec_avmm2_avmmread_in" File: D:/intelFPGA_pro/Project /stratix10TX_1st280yf55_si_revB_v18.1.2b277_v1.0/examples/qts_pam4_com/pam4_xcvr_com_19.3/qts_pam4_com/pam4_xcvr_com.v Line: 130
Info (16867): Verilog HDL info at nphy.v(6): nphy is declared here File: D:/intelFPGA_pro/Project/stratix10TX_1st280yf55_si_revB_v18.1.2b277_v1.0/ examples/qts_pam4_com/pam4_xcvr_com_19.3/qts_pam4_com/nphy/synth/nphy.v Line: 6

Comment out the following because the ports that were in the past version of E-Tile nativePHY remain in the top level of the design.

 .rsfec_avmm2_avmmread_in ( ), // input, width = 1, RSFEC_avmm2.read 
.rsfec_avmm2_avmmrequest_in ( ), // input, width = 1, .waitrequest 
.rsfec_avmm2_ avmmwrite_in ( ), // input, width = 1, .write

Also, the IO Standard for pll_refclk0 and pll_refclk1 was compiled with LVDS in past versions, but if it does not work with your version, please change it to Differential LVPECL.

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Category: Development Kits / Transceivers
Tools: Quartus® Prime
Devices: Stratix® 10