Introduction.
Have you ever run Quartus® Prime development software timing analyzer and found that timing errors do not occur, but when you compile the software, it malfunctions?
In this case, one of the possible causes may be that the SDC constraints are not described correctly.
Check to see if the SDC file you created has been properly registered with Quartus
In Quartus® Prime development software, select Assignments menu -> Settings... in Quartus® Prime development software, and select Timing Analyzer from Category:.
If the SDC file is not listed, add it.
If your design incorporates IP, make sure the qip file is registered.
(The SDC file is registered in the qip file.)
(The SDC file is registered in the qip file.) *Reference:Registration order for multiple SDC files to be registered with Quartus® Prime development software
(2) Check for undefined clock paths
Select Tools menu -> Timing Analyzer.
From the Tasks pane, double-click Report Unconstrained Paths to execute.
After execution, a summary is displayed in the View pane.
Click Clock Status Summary in the Report pane to see the details of the path in the View pane.
If there is an undefined clock, it is displayed in red, so set the correct clock frequency.
(iii) Check for ignored clock constraints.
Incorrect clock constraints may have been given due to misspelling or misrecognition of clock signals.
In such cases, you can double-click Ignored Constrains in the Tasks pane to check.
What do you think?
Even if you think you have set the clocks correctly, please be aware that the clock settings may be ignored or scaled due to changes in clock configurations as the specification changes and RTL is modified.