SoC FPGA Bare Metal All-in-One Application Samples

Notice.
We have updated the sample projects for the latest version of the tool environment "Quartus^® Prime Standard Edition Development Software v22.1, Arm^® Development Studio (Arm DS) 2022.2". (2023.03.23)

Introduction

This sample is intended as a starting point for building bare-metal applications for Altera^® ( Intel^® ) SoC FPGAs.

The code required for bare-metal development, such as the Hardware Library (HWLib), is preinstalled in the project and included in the build target, allowing users to use the API without having to edit the Makefile by simply including the necessary header files. In addition, unused APIs can be removed from the Makefile.

Unused APIs are excluded from the linking process, so code size is not affected.

The attached document explains the following

• Usage environment (supported versions, supported boards)
• Advantages of using this sample
• Directory/file structure of the sample
• Compilation settings
• Basic operation of the sample
• How to add commands
• Description of the sample's main routines and source code
• Introduction of useful utility functions
• What is HWLib (Hardware Library)
• HWLib Examples

Advantages of using this example

In a typical bare-metal sample application, only the HWLib for the appropriate interface is configured to be used, and the Makefile must be modified to specify additional HWLib sources in order to use the other HWLibs.

Also, since the HWLib is provided in a Makefile project, any additional source files added by the user must be appended to the Makefile, which is time-consuming to understand for those who are not familiar with the SoC FPGA software development flow.

In this sample, all the sources provided as HWLib are already registered, and all the APIs can be used by including the HWLib header file you want to use.

In addition, all source files added to the project's TOP directory are made compile-ready, so you can basically start various evaluations without modifying the Makefile.

Usage Environment

This section describes the development environment and supported target boards. For more detailed information, please refer to the attached documentation (.pdf).

Development Environment

The main development environment used in the description in the attached document is shown below. This sample project has been tested using the following environments.

Table 1. Main development environments used in the attached document

Item No.	Item	Latest version (Ver22.1/for Arm DS)	Previous version (for Ver20.1/Arm DS)	Previous version (Ver18.1/for DS-5)
1	Host PC	64 bit machine with Microsoft® Windows® 10 (64 bit)	64 bit machine with Microsoft® Windows® 10 (64 bit)	64 bit machine with Microsoft® Windows® 7 Professional SP1 (64 bit)
2	Quartus® Prime Development Software Standard Edition (hereafter referred to as Quartus® Prime) * A tool for developing hardware for SoC FPGAs.	Use Quartus® Prime Standard Edition Development Software v22.1. Quartus® Prime Standard Edition v22.1  Reference: For Quartus® Prime installation instructions, please refer to the following website : Quartus® Prime & Questa* Installation Instructions (In Japanese) Note: You must install the Device Data corresponding to the SoC FPGA on the target board you are using. Note: In this document, only Quartus® Prime Programmer is used to download the hardware design (sof file) to the FPGA in section 4-6, FPGA Configuration.	Use Quartus® Prime Standard Edition Development Software v20.1. Quartus® Prime Standard Edition v20.1 Note: For instructions on how to install Quartus® Prime, please refer to the following site Quartus® Prime & ModelSim® Installation Instructions (v18.0) - Macnica (macnica.co.jp) Note: You must install the Device data corresponding to the SoC FPGA on the target board you are using. Note: In this document, only Quartus® Prime Programmer is used to download the hardware design (sof file) to the FPGA in section 4-6, FPGA Configuration.	Use Quartus® Prime Development Software Standard Edition v18.1. Quartus® Prime Standard Edition v18.1 Note: For instructions on how to install Quartus® Prime, please refer to the following site Quartus® Prime & ModelSim® Installation Instructions (v18.0) - Macnica (macnica.co.jp) Note: You must install the Device data corresponding to the SoC FPGA on the target board you are using. Note: In this document, only Quartus® Prime Programmer is used to download the hardware design (sof file) to the FPGA in section 4-6, FPGA Configuration.
3	SoC FPGA Embedded Development Suite Standard Edition (hereafter referred to as SoC EDS) * Tools for developing software for SoC FPGAs.	Point: The sample projects in this version can be used without installing SoC EDS. (See the attached document for details) If you are using SoC EDS Standard Edition v20.1, you can obtain it from SoC EDS Standard Edition v20.1 Arm DS allows you to compile and debug your application software. Reference: For information on how to install SoC EDS and Arm DS, please refer to the following site How to install SoC FPGA Embedded Development Suite (SoC EDS) ver. 20.1 NOTES: Debugging bare-metal applications using the Intel® FPGA Download Cable II (hereafter USB-Blaster™ II) requires Arm DS / DS-5 (paid version). NOTES: This version of the sample projects assumes the use of the Arm DS; if you wish to use them with the DS-5, please use the previous version of the sample projects.	Use SoC EDS Standard Edition v20.1. SoC EDS Standard Edition v20.1 In addition to SoC EDS, you will need to install Arm® Development Studio Intel® SoC FPGA Edition ("Arm DS"). Arm DS allows you to compile and debug your application software. Reference: For information on how to install SoC EDS and Arm DS, please refer to the following site. How to install SoC FPGA Embedded Development Suite (SoC EDS) ver. 20.1 NOTES: Debugging bare-metal applications using the Intel® FPGA Download Cable II (hereafter USB-Blaster™ II) requires Arm DS / DS-5 (paid version). NOTES: This version of the sample projects assumes the use of the Arm DS; if you wish to use them with the DS-5, please use the previous version of the sample projects.	Use SoC EDS Standard Edition v18.1. SoC EDS Standard Edition v18.1 The Arm® Development Studio 5 Intel® SoC FPGA Edition (DS-5) included with SoC EDS can be used to compile and debug application software. Reference: For information on how to install SoC EDS, please refer to the following site How to Install SoC FPGA Embedded Development Suite (SoC EDS) ver. 18.1 - Macnica (macnica.co.jp) NOTES: Debugging bare-metal applications using the Intel® FPGA Download Cable II (hereafter USB-Blaster™ II) requires DS-5 (paid version).
4	Terminal Emulation Software	Serial terminal software is required to use this sample. In this document, freeware software called "Tera Term" is used. Download URL of Tera Term NOTES: In Tera Term, make the following settings for the valid COM port when connecting to the UART on the target board. ・ Baud rate 115200 bps ・ 8-bit data ・ No parity ・ 1 stop bit ・ No flow control	Same as on the left.	Same as on the left

Note: If build errors occur, please also check the following information

• Workaround for sopc-create-header-files execution error in SoC EDS environment
• Workaround for bsp-create-settings execution error in SoC EDS environment

Supported target boards

In this sample, the following target boards can be specified by TARGET_BOARD in the config.mk file.

Table 2] Supported target boards in this sample

Item No.	Target board
1	Cyclone® V SoC Development Kit
2	Arria® 10 SoC Development Kit
3	Helio - Cyclone® V SoC Kit (Discontinued)
4	Sodia - Cyclone® V ST SoC Evaluation Board
5	DE0-Nano-SoC Kit / Atlas-SoC Kit (Discontinued)
6	DE10-Nano Kit

Note: Sample projects for Ver20.1 and later do not include data for Helio boards; if you wish to use them with Helio, please use the sample projects for Ver18.1.

Documents/Sample Projects

Note: .pdf with _EN at the end of the file name is automatically translated into English. The English translation of the latest version is attached. Previous versions are only in Japanese.

📕 Documentation

SoCFPGA_HWLib-All-In-One_v221_r4_EN.pdf
Explanatory Material ver22.1 (rev.4) (In English)

SoCFPGA_HWLib-All-In-One_v221_r4.pdf
Explanatory Material ver22.1 (rev.4) (In Japanese)

SoCFPGA_HWLib-All-In-One_v201_r3.pdf
Explanatory Material ver20.1 (rev.3) (In Japanese)

SoCFPGA_HWLib-All-In-One_v181_r1.pdf
Explanatory Material ver18.1 (rev.1) (In Japanese)

📦 Sample Projects

ALT-HWLib-All-In-One_v22.1_r4.0.tar.gz
Bare-metal sample application (Arm DS 2022.2 compliant version)

ALT-HWLib-All-In-One_v20.1_r3.3.tar.gz
Bare Metal Sample Application for Arm DS 2020.1

ALT-HWLib-All-In-One_v18.1_r1.4.tar.gz
Bare Metal Sample Application