* The original content was created in Japanese, so some information, images, and links may still be in Japanese. We’re updating gradually and appreciate your patience.
Introduction
There are as many ways to deal with timing convergence as there are user designs.
This article presents a general flow to help designers find a solution to timing convergence.
As you follow the steps, try to find a solution that fits your design.
Step 1 Check before analysis
Check the validity of the SDC with reference to the following article.
This is the most important step because it will be meaningless to proceed to the next step if the timing constraints are inconsistent with your specifications or design, or if the timing converges with no valid timing constraints.
- Points to Look at First When Performing Timing Analysis
- Reference material: Quartus® Beginner's Guide - Timing Constraint Method
Step 2 Perform timing analysis
Perform timing analysis and iteratively test the settings to ensure that they are appropriate for the design. Timing analysis is user-project dependent and should be performed by the user.
- Reference AN 584: Timing Closure Methodology for Advanced FPGA Designs
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Reference: Quartus® Prime Getting Started Guide - How to Perform Timing Analysis with TimeQuest (Japanese)
(p20 5. Methods for Improving Timing Errors) - Reference: TimeQuest - Timing Analysis Terminology and Concepts (Japanese)
Step 3 Try Timing Optimization Advisor settings
Try Timing Optimization Advisor settings.
(Please use Design Assistant for v21.1 pro edition or later. (Reference KDB: ID: 000086071)
Step 4 Explore seeds and settings in Design Space Explorer (DSE)
Use Quartus® Prime's DSE feature to automatically search for optimal settings.
- Reference: Quartus® Guide - How to Use Design Space Explorer II
- Reference Material: 12. Design Space Explorer
Timing Related Documents
- Reference: Quartus® Prime Pro Edition User Guide
- Reference: TimeQuest Timing Analyzer Resource Center
- FAQ Article: Are there any items in Quartus II that could be configured to improve performance? (Japanese)
Related Online Seminars
- Macnica: [Online Seminar] Timing Analysis for FPGAs - Introduction <Free> (Japanese)
- Macnica: [Online Seminar] Timing Analysis of FPGAs - Beginner's Level - <FREE> (Japanese)
Please refer to it.
(*) TimeQuest is the former name of the current Timing Analyzer