[RTL Design Beginner's Guide] Difference between Synchronous and Asynchronous Design

Unlike ASSPs, which have a fixed purpose and function, FPGAs and CPLDs allow designers to freely incorporate only the functions they need.

Just like painting a picture on a blank canvas, designers build (design) logic circuits into an empty box (although the box is not actually empty). Because the designer can design freely, if the RTL designer does not organize and establish the correct design method for FPGAs and CPLDs and understand their characteristics, unstable situations such as "It worked in simulation, but it did not work on the actual device" or "It worked when the device was cooled down" can occur. These are almost always due to timing issues. In other words, "unreliable logic circuits are implemented.

To build reliable logic circuits, it is important to learn the basics of design techniques that are the key to RTL design of FPGAs and CPLDs.

In this article, before introducing the description techniques, we would like to discuss the difference between synchronous and asynchronous design in digital logic circuit design.

This is a must for users who are doing FPGA / CPLD RTL design for the first time.

FPGA/CPLD design is all about synchronous design!

This is not limited to Intel FPGAs and CPLDs, but is common to all FPGA / CPLD manufacturers. To understand this, let's first understand the advantages and disadvantages of synchronous and asynchronous circuits.

What is a synchronous circuit?

A synchronous circuit is a circuit system that operates synchronously with the same edge of the same clock.

Therefore, even if they are the same clock, they are not regarded as the same clock when edges of opposite phase are used.

Basically, a single clock synchronization is desirable. Transferring signals between different clocks is an asynchronous circuit and requires appropriate processing for asynchronous inputs.

Advantages of Synchronous Circuits	Disadvantages of synchronous circuits
Timing is easy to obtain. Glitch-free system can be configured High-speed operation is possible Easy to debug	Large power consumption Circuit size tends to be large

Design examples of synchronous design are shown in VHDL and VerilogHDL.

VHDL

VerilogHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity s_counter is
port (
clk : in std_logic;
enable : in std_logic;
q : out std_logic
);
end s_counter;

architecture sync_pld of s_counter is
begin

process (clk)
variable cnt : std_logic_vector(2 downto 0);
begin
if enable = '0' then
cnt := cnt;
elsif (rising_edge(clk)) then
cnt := cnt + 1;
end if;
q <= cnt(2);
end process;

end sync_pld;

module s_counter (clk, enable, q);
input clk, enable;
output q;

reg [2:0] cnt;

always @(posedge clk)
if (enable)
cnt = cnt+1;
else
cnt = cnt;

assign q = cnt[2];

endmodule

What is an asynchronous circuit?

An asynchronous circuit is a circuit system that does not operate synchronously on the same edge of the same clock.

Therefore, circuits that operate on different clock edges of the same clock are asynchronous circuits.

A ripple clock is the best example. Reusing an internally divided output is also an asynchronous clock compared to the source clock.

Advantages of asynchronous circuits	Disadvantages of asynchronous circuits
Small circuit size Low power consumption	Timing is difficult to obtain. Low operating frequency Timing simulation is difficult

Design examples of asynchronous design are shown in VHDL and VerilogHDL.

VHDL

VerilogHDL

library ieee;
use ieee.std_logic_1164.all;

entity a_counter is
port (
clk : in std_logic;
enable : in std_logic;
q : out std_logic
);
end a_counter;

architecture async_pld of a_counter is
signal cnt2, cnt1, cnt0: std_logic:='0';
begin
q0:process (clk) begin
if (enable='0') then
cnt0 <= cnt0;
elsif rising_edge (clk) then
cnt0 <= not cnt0;
end if;
end process q0;

q1:process (cnt0) begin
if rising_edge (cnt0) then
cnt1 <= not cnt1;
else
cnt1 <= cnt1;
end if;
end process q1;

q2:process (cnt1) begin
if rising_edge (cnt1) then
cnt2 <= not cnt2;
else
cnt2 <= cnt2;
end if;
end process q2;

　q <= cnt2;

end async_pld;

module a_counter (clk, enable, q);
input clk, enable;
output q;

reg cnt0, cnt1, cnt2;

always @(posedge clk) begin
if (enable)

cnt0 = ~cnt0;
else

cnt0 = cnt0;
end

always @(posedge cnt0)
cnt1 = ~cnt1;

always @(posedge cnt1)
cnt2 = ~cnt2;

assign q = cnt2;

endmodule

An example design using a reverse phase clock is shown in the VHDL and VerilogHDL descriptions.

VHDL

VerilogHDL

library ieee;
use ieee.std_logic_1164.all;

entity rev_clk is
port (
clk : in std_logic;
data : in std_logic;
q : out std_logic
);
end rev_clk;

architecture rev_clk_pld of rev_clk is
signal int0, int1: std_logic;

begin
process (clk) begin
if (rising_edge(clk)) then
int0 <= data;
else
int0 & lt;= int0;
end if;
end process;

process (clk) begin
if (falling_edge(clk)) then
int1 <= int0;
else
int1 <= int1;
end if;
end process;
q <= int1;
end rev_clk_pld;

module rev_clk (clk, data, q);
input clk, data;
output q;

reg int, q;

always @(posedge clk)
int = data;

always @(negedge clk)
q = int;

endmodule

In light of the above

The basic idea to ensure high design quality of systems using FPGAs and CPLDs is synchronous design with a single clock.

As FPGAs/CPLDs become larger, various interconnect schemes have been proposed by device vendors to ensure flexibility while maintaining high speed.

However, it is practically impossible to arrange the delays within any one device to be uniform throughout the entire device. Furthermore, these delays often vary due to external factors such as voltage fluctuations, ambient temperature, and lot-to-lot variations.

Asynchronous design under these conditions creates competition between the clock and data signals. Sometimes, a "skip" situation occurs where the data overtakes the clock.

To prevent this from happening, a synchronous design must be performed while maintaining the worst-case conditions recommended by Intel. As long as the synchronous design is adjusted to minimize clock skew in the device, there is no need to worry about "missing" clocks.

Therefore, the only thing you need to worry about is ensuring the setup time and hold time of the external input signal.

I hope that you will keep these points in mind as you build a more reliable digital logic circuit design.
In this article, I explained synchronous and asynchronous circuits, which are the basics of FPGA / CPLD design.

FPGA/CPLD design is all about synchronous design!

What is a synchronous circuit?

What is an asynchronous circuit?

In light of the above

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