Here is a brief description of the hazard signals that may have troubled digital circuit designers, the simple mechanism of why they occur, and how they affect the system.
Things that may trouble digital circuit designers
Electrically normalized logic circuits have been built in a variety of implementations, including custom LSIs, standard cells, ASICs, FPGAs, CPLDs, and even TTL in the past. Compared to analog signals, logic signals are normalized and therefore very simple to think about. This simplicity has dramatically improved our current civilization. It is no exaggeration to say that we have come to an age in which most physical phenomena in nature are digitized and even computerized.
While many conveniences are offered, at the stage when they are actually systematized using semiconductor circuits, they can be thought of macroscopically as normalized digital circuits (logic circuits), but microscopically as analog signals. In particular, recent semiconductor devices have become so fast that we can no longer think of logic circuits in terms of simple "1s" and "0s. For example, high-speed transmissions in the gigahertz (GHz) band and the weakening of the signals handled for low power consumption are examples.
In this world that cannot be closed only by the simple "1" and "0" world, signals other than the expected value, which have long been called " hazards," have been included in the original logic signals, called "hazards," and logic circuit designers have often been troubled by them.
Hazard signals are
Hazard is a malfunction of a circuit that causes the output to differ from its normal value when one or more inputs are changed.
Types of Hazards
There are two types of hazards: Dynamic Hazard and Static Hazard.
A Dynamic Hazard is a phenomenon in which a change in one or more inputs causes a change in the output, which changes three or more times and generates a series of transient values.
For example, when transitioning from “1” to “0” ; "1" → "0" → "1" → "0". For example, when the transition is from "0" to "1": "0" → "1" → "0" → "1".
Static hazard is when one or more inputs change and the outputs that should take the same value temporarily take a value different from the correct value. There are two cases of static hazard.
1 Hazard: A "1" output temporarily becomes a "0".
0 Hazard: "0" output becomes "1" temporarily.
Mechanism of Static Hazard
This section describes static hazards.
The figure below shows a commonly used signal switching circuit (MUX).
In the example above, the delay (d) of the inverter for the switching signal is much larger than the delay (δ) of other AND-OR gates, for ease of understanding.
Considering this example, for example, when inputs A and B are "1", nothing should occur at the output when the switching signal S is switched, but if the delay (d) of the inverter making S' is sufficiently larger than the delay (δ) of the gate If the delay (d) of the inverter making S' is sufficiently large compared to the delay (δ) of the gate, there will be a considerable time lag between the change in signal S and the change in S'. In such a case, even if S changes from "1" to "0" and the p-point output becomes "0", the S' signal is not yet "1". Therefore, the output at point q also remains "0" as a result. Therefore, "0" is output at the final output point Z.
This negative pulse (corresponding to delay d) is the static hazard. This hazard is caused by timing deviations of multiple signals.
This timing gap is not uniquely determined (as will be explained later), but is affected by various environments. Even if it is not occurring at this moment, it may appear at any time. Therefore, it is necessary to design a system that explicitly suppresses the cause of the occurrence.
Suppression of Static Hazard Signals
Static hazards occur when there is a time lag between changes in two or more inputs. In other words, to eliminate static hazard, only one input should be allowed to change. A common way to avoid static hazard is to add redundant circuits. A Karnaugh diagram is used to find a suitable redundant circuit.
The left figure below shows a Karnaugh diagram, and the right figure below shows an example of adding redundant circuits to the previous diagram to suppress static hazards.
To create a Karnaugh diagram, write input variables on the X and Y axes. As mentioned earlier, if only one input changes, no hazard is generated, so to examine this, we arrange the variables so that only one variable changes. In the case of the switching circuit (MUX) described earlier, the variables are A, B, and S. Therefore, the two variables of AB on the X-axis are arranged so that they change by one bit: "00" → "01" → "11 " → "10", and on the Y-axis, S is arranged as "1" → "0". Then fill in the table with the output Z for each input. In this example, the input switching signal S is "1" when input AB is "11" and "10", and S is 0" is when AB is set to "01" and "11".
In the above left diagram (Karnaugh diagram), the terms with two "1 "s next to each other in the column for the switching signal S are the required terms indicating the normal output terms AS and BS'. If we now look at the neighboring input states whose outputs are "1" and which differ by only one input value, we see that if S is "1", AS continues to define Z as "1 " when S is "0", and when S is "0", BS' continues to define Z as "1" even if A changes, so there is no hazard. However, the change in S is not included in the normal term. This is the cause of the hazard. Therefore, by adding the AB term ("11"), the hazard can be eliminated because the AB term continues to define Z as "1" even for changes in S. Since this term is not a required term, it is deleted in general logic synthesis, but it is necessary from the viewpoint of hazard prevention. Therefore, if redundant functions are explicitly described in the source for the purpose of preventing hazards, it is necessary to set that section to not compress logic.
Effects of Hazard Signals on the System
Normalized logic signals exist invisibly in the realized electronic circuit. This signal may be difficult to observe even with instrumentation. In particular, they are impossible to observe with logic analyzers used for logic circuit observation. Even equipment for waveform observation, such as oscilloscopes, must be quite expensive. In addition, wisdom and skill are required for hazard observation.
Is it unstable in the summer?
Especially bad is the fact that equipment tested in a favorable environment (stable power supply, air-conditioned room, etc.), such as a laboratory or manufacturing plant, will generally operate in a stable manner. The word "operate" is used because in most cases, the devil (hazard) does not appear in a favorable environment. If the problem occurs in the laboratory or at the factory inspection stage, it can be dealt with before shipping to the market. However, these demons (hazards) are mean, and as soon as they go to a bad environment, such as an unstable power supply or high or low temperatures, which are considered easy for them to live in, they will show their faces. Have you ever experienced that your equipment became unstable in the summer, or that your equipment became unstable when the production lot was changed? The main cause of this is the hazard (devil).
Is the latest lot unstable?
This hazard is caused by changes in the timing of devices due to changes in the environment. In particular, in the world of FPGAs and CPLDs, the manufacturing process is constantly evolving, even though they have the same type name. While other semiconductor logic devices generally use the same manufacturing process for their entire life, in the FPGA and CPLD worlds, process miniaturization is used to improve yields and increase speed, which tends to accelerate device delays. As a result, differences in timing between signals occur, inducing hazards. In particular, in the case of devices with large lifetime lots that are produced repeatedly over many years, problems may occur where "no problems occurred in past production lots" but "the latest lot is unstable. In such a case, it is easy to fall into the trap of problem resolution. One problem-solving approach that is often taken in such cases is to not look at the design review, saying that there is no problem in the design because it has been working properly in the past. In such cases, the problem-solving approach becomes a stopgap measure, and the same problem may occur later.
Causes of Hazards and Remedies
The causes of this timing deviation can also be caused by fluctuations in supply voltage or changes in the operating temperature of the environment in which the equipment is installed.
1. fluctuations in power supply voltage
2. fluctuations in ambient temperature
3. changes in the manufacturing process.
Although the impact of hazards on the system is often immeasurable, it is recommended that the following measures, including the "hazard deterrent" mentioned above, be adopted to resolve these instabilities in the system.
1. clock synchronization to avoid the hazard in the register circuitry
2. register latch output of output signals
3. Hazard prevention by using redundant circuits
Finally
In general, the phenomenon of hazard is almost always undetectable by simulation or measurement instruments. Therefore, it is important to assume that "circuits generated by electronic circuits always generate hazards," and to configure "circuits that have no problem even if hazards do occur. For this reason, synchronous design is still an important point.
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