Even though the equipment has been designed and evaluated as a matter of course, we sometimes hear that the equipment sometimes malfunctions when connected to other equipment, or that it malfunctions during the hot summer months. These causes are mostly due to timing effects, input signals that are not synchronized with the system (asynchronous input signals), and hazards that occur in the circuit.
In this issue, we will discuss the effects of input signals that are not synchronized with the system on the system and how to solve these problems.
Asynchronous Input
The Meaning of Asynchronous Inputs
In FPGAs, there are setup time (tSU) and hold time (tH) stipulations between flip-flop input signals and clock signals as requirements for stable operation. Digital logic circuit designers must strictly adhere to these stipulations. These requirements are stored in the development software provided by the FPGA manufacturer. Figure 1 shows a conceptual diagram of setup time and hold time.
Violation of the setup time/hold time rule can result in a temporary unstable state called "metastable" or a state different from the system-defined state. This can have a significant impact on system reliability. When data is exchanged between different devices, the system is asynchronous, and this setup and hold time cannot be guaranteed between the signals received and the system clock. Signal synchronization is required when signals are exchanged between these devices, and failure to synchronize can easily lead to metastable conditions (metastability). （Metastability does not always occur. Even when they do occur, they are usually of the order of ns in duration, so they may not cause problems. However, with extremely low probability, metastable instability can cause long periods of instability.)
What is a metastable?
A metastable is a state in which the output state does not stabilize even after the originally specified output time tCO from the clock is exceeded. The time tMET required to stabilize depends on the ambient conditions and the manufacturing technology of the device.
The behavior of a register can be represented by comparing it to a ball moving along a frictionless mountain, as shown in Figure 2. Both sides of the mountain represent stable states (High or Low), and the top of the mountain represents the state of the metastable.
If the input to the flip-flop satisfies the specified minimum setup time tSU and minimum hold time tH, the output changes from one stable state to the other (from High to Low or Low to High) with no additional delay.
On the other hand, if the data input to the flip-flop violates the stipulated setup time or hold time, the flip-flop may not be triggered in its entirety and the output may not immediately transition to one of the two stable states within the stipulated time. This improper triggering can cause the output to glitch or temporarily put the output in a metastable state between High and Low, causing the output to take longer to return to a stable state, increasing the time between clock transitions and output stability under either condition.
Metastability is not necessarily a factor that makes system performance unpredictable. If the flip-flop is allowed enough latency to return to a stable state, system performance will not be affected, and even if the flip-flop output becomes temporarily indeterminate, this signal can return to a stable state before it is actually used. Thus, by allowing an additional time tMET for the signal to settle to a pre-specified value, it is possible to avoid propagation of signals of an unspecified value to other parts of the system.
Impact of Metastability on the System
As mentioned earlier, asynchronous inputs have a negative impact on the system. Basically, once a flip-flop in the system enters a metastable state, it is not only unstable, but in the worst case scenario it can lead to a system hang-up. The only way to recover is to turn off the power. Thus, the metastable state cannot be artificially defined from the system. Only the physical properties of the semiconductor can control the state. Only God knows.
A particularly easy case to fall into is the case of systems with identical clocks. For example, two devices running on the same 50 MHz master oscillator can exchange signals with each other. Even with nominally identical frequencies, the two master oscillators have different frequency deviations, temperature coefficients, and so on, resulting in subtle frequency fluctuations. As a result, the signals are mutually asynchronous. Please be aware of this.
Metastability Workaround
The two most common ways to reduce the effects of metastability are
- Use synchronous flip-flops
- Use FIFO logic
These are briefly described below.
Use of synchronous flip-flops
A common metastable measure is to insert several synchronization flip-flops in the rear receiver clock domain to synchronize the asynchronous input signals with the system clock, as shown in Figure 3. However, although the number of flip-flops inserted significantly improves system reliability, the number of inserted flip-flop stages increases system latency, which may cause performance degradation in the overall system.
If the difference between the repetition frequency of the asynchronous input signal and the frequency of the system clock is negligible, one stage is sufficient, but if the two frequencies are adjacent, several stages may be inserted. To determine how many stages should be inserted, check the MTBF (mean time between failures) using Quartus® Prime's TimeQuest timing analyzer function. It is recommended to shorten the time between FFs on the receiving side to shorten the metastable period.
In Figure 3, even if the synchronizing flip-flop (the first flip-flop) generates a metastable output, the metastable signal will then have the possibility to stabilize before the second flip-flop is triggered. This method does not guarantee that the second flip-flop will not trigger an unstable output, but it does improve the probability that the data will be valid before it reaches the rest of the circuit. In this way, the required reliability of the system determines the number of flip-flop stages to be inserted.
In any case, do not feed a single asynchronous input to multiple flip-flops; feeding a single asynchronous input to multiple flip-flops increases the probability of system error due to metastable conditions. This is because if an asynchronous input signal is fed to multiple flip-flops, each connected flip-flop may be in a different state, making it impossible to define a unique state in the system. In such a case, please include a synchronizing flip-flop and supply the output to the subsequent flip-flop or logic after defining the state uniquely in the system.
Use of FIFO Logic
To synchronize multiple bits of input, such as a data bus, simultaneously, use First-In First-Out (FIFO) logic, which uses a synchronizer to transmit control signals between two clocks, and data to a dual-port memory Data is read/write to the dual-port memory. Figure 4 shows its schematic.
Finally.
When an asynchronous signal is input to the system, it causes an unpredictable system condition called a metastable. In the worst case, this can cause the system to hang and not recover until power is disconnected. Metastable conditions can occur when signals are exchanged between devices that are not synchronized throughout the system. Therefore, it is recommended that the entire system's signal chain be scrutinized to establish a synchronized system and remove any unstable elements.
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