Metastable signals from different clock domains ( CDC ( Clock Domain Crossing ) ) have become an issue in today's FPGA designs. Traditional structure-based verification alone is not effective in verifying CDC signals. This column explains the CDC problem and its verification method in four parts.
Part 1: What are setup time and hold time?
Part 2: What is a metastable?
Part 3: Common metastable measures and their problems
Part 4: How to verify metastables
Part 4: How to Verify Metastable
In my previous column, I explained that it is very difficult to verify metastables.
This time, we will introduce a tool we recommend for verifying the metastables.
4-1 Questa®CDC from Mentor Graphics
Questa CDC is a tool that supports all three basic elements required for CDC verification: structural analysis, protocol verification, and reconvergence verification. Analysis can be performed at the stage where RTL is completed before logic synthesis.
4-2 Features of Questa CDC
1. All CDCs can be analyzed at RTL before logic synthesis.
2. CDC structure analysis results are reported in categories considering countermeasures. 3.
3. The corresponding CDC location can be displayed in the circuit diagram from RTL.
Assertion can be automatically generated from the structural analysis result to the part where protocol verification is required. 5.
5. Reconvergence verification can be performed by automatically generating a circuit that creates a metastable state.
6. Verify the effectiveness of CDC measures taken.
(7) Testbench creation is not required if a random testbench generation function such as Questa is used.
(8) A kit to support FPGA verification is included.
9. The operation method is simple and easy-to-use.
4-3 Functions of Questa CDC
The functions of Questa CDC are introduced below.
(1) Structure analysis
Questa CDC analyzes the structure from RTL and reports CDC locations.
Even if there are CDC points, there is no need to modify RTL if there is no influence. However, since the error locations by structural analysis can be as many as several thousand, it is important to have a report that is easy to analyze and to be aware of the measures to be taken.
Questa CDC provides structural analysis reports by CDC technology (FIFO/D-MUX/Multi-FF/HandShake, etc.), by bus/single, and by whether verification is unnecessary or not, so you can know what to do next even if you are not familiar with CDC countermeasures. This report is very useful for designers because CDC measures vary depending on circuits and specifications.
Just by looking at the report, you can find out the following
The following can be identified just by looking at the report:
・Parts where synchronizers are not included ・Parts where synchronizers are not included correctly
・Parts where synchronizers are included but protocol verification is required
・Parts where synchronizers are included but protocol verification is not required
・Parts that are excluded from verification on the user side
・Parts where CDC verification is not required due to configuration circuits, etc. Locations where CDC verification is not required, such as configuration circuits.
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CDC Summary |
Figure 4-1. Example of CDC report
Since there is a function that automatically displays the CDC points from RTL on the schematic, it is useful when analyzing from the report contents.
Figure 4-2. Example of automatically generated schematic
(2) CDC Protocol Verification
For protocol verification, which is difficult to determine whether or not CDC measures are necessary by only checking the structure, logic simulation is performed to verify it.
Questa CDC automatically generates a checker (assertion description) for protocol verification, so by using a logic simulation that supports assertions, such as ModelSim® DE or Questa, it is possible to verify whether the CDC signal is stable during the period when data can be reliably transferred from the clock ratio of the transmitting and receiving sides. is stable for a period of time during which data can be reliably transferred based on the ratio of clocks on the transmitter and receiver sides.
For more information on assertions, click here.
The tool automatically generates a checker (assertion description) for each synchronizer.
With Quest's random testbench generation, you can verify whether protocol errors occur in a fully automated manner.
The checker also includes coverage information so you can manage the validity of your testbench and the progress of your verification when using random simulation.
Figure 4-3. Protocol Error
(3) CDC Reconvergence Verification
Reconvergence is difficult to verify. It cannot be verified by ordinary logic simulation or actual device.
Questa CDC can verify the effect of CDC reconvergence by intentionally inverting the logic at the clock timing when metastable is about to occur (near miss), as if metastable occurred.
Figure 4-4: Structure of Reconvergence Verification
As shown in the figure above, a circuit called a metastability injector is automatically generated and inserted based on the results of CDC structural analysis, so that metastable tolerance verification can be fully automated by combining it with Questa's random test.
In ModelSim, a testbench for function verification can be used to verify if the effect of the reconvergence on the output pins can be verified by comparing the waveforms before and after the CDC countermeasure.
Thus, Questa CDC from Mentor Graphics supports all three basic elements required for asynchronous transfer (CDC) verification solutions that are difficult to verify using conventional verification methods: structural or static CDC analysis, CDC protocol verification, and CDC reconvergence verification. structural or static CDC analysis, CDC protocol verification, and CDC reconvergence verification.
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