Metastable signals from different clock domains ( CDC ( Clock Domain Crossing ) ) have become an issue in today's FPGA designs. Traditional structure-based verification alone is not effective in verifying CDC signals.
This column explains the CDC problem and its verification method in four parts.
Part 1: What are setup time and hold time?
Part 2: What is a metastable?
Part 3: General metastable measures and their problems
Part 4: How to verify metastables
Part 3: General metastable measures and their problems
As shown in Figure 3-1, a general metastable countermeasure is to insert two or more FFs in the rear receiving clock domain. Recently, three or more stages are often inserted. To determine how many stages should be inserted, check the MTBF (mean time between failures) using the Quartus® II TimeQuest timing analyzer function. It is recommended to shorten the time between FFs on the receiving side to shorten the metastable period.
Figure 3-1 General metastable measures
By inserting several FFs, it is possible to suppress the transmission of metastable signals to the next stage. However... the problem still remains. Protocol and reconvergence issues.
Protocol Errors
In the waveform shown in Figure 3-2, the first-stage FF is metastable on the first clock, so the logic at the output of the first-stage FF (Q1) is not stable. Then, the second-stage FF takes the data (Q1) and sets the output (Q2) to Low (0), so the metastable is not propagated to Q2.
However, since the data changed after the second clock cycle, the first cycle of data has been missed in this case. This is a protocol error.
Even if the metastable is bypassed, it is useless if no data is retrieved. To prevent protocol errors, data (D) must be kept stable until the second-stage FF can receive data.
Figure 3-2 Protocol Errors
Reconvergence Error
What if the data is fetched after it has stabilized to avoid causing a protocol error, but this is the Bus?
The bits that metastable are transferred in the next clock cycle (2-cycle transfer), and the other bits that do not metastable are transferred in the previous clock cycle (1-cycle transfer).
The failure caused by this is a reconvergence error.
Figure 3-3 Reconvergence
Are you taking measures to prevent recurrence errors?
That's all for this issue. In the next article, we will explain how to verify metastables.
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