Metastable signals from different clock domains ( CDC ( Clock Domain Crossing ) ) have become an issue in today's FPGA designs. Traditional structure-based verification alone is not effective in verifying CDC signals. This column explains the CDC problem and its verification method in four parts.
Part 1: What are setup time and hold time?
Part 2: What is a metastable?
Part 3: General metastable measures and their problems
Part 4: How to verify metastables
Part 1: What are setup time and hold time?
All FFs (flip-flops)/registers incorporated in LSIs such as FPGAs and ASICs have defined timing constraints such as setup and hold times so that each of them can correctly take data at the time of input and generate output signals.
In other words, the input data must be stable for a minimum time before the edge of the clock (setup time tCO) and a minimum time after the edge of the clock (hold time tH).
I would like to explain the reason for the setup and hold time constraints from the D-FF (flip-flop) structure. To briefly explain the D-FF structure to those who are not interested in it, if the data is not stable before and after the clock is turned on, not only will you not know which data to take before or after If the data is not stable before and after the clock is turned on, not only will you not know which data to take before or after, but you will also experience a metastable condition where the output stays at a potential between "Low(0)" and "High(1)" for a while. This is where the setup/hold time constraint exists.
Let us explain this phenomenon in detail.
There are various structures of D-FF (flip-flops), but in CMOS circuits, they are generally composed of inverters and transfer gates as shown in Figure 1-1. Although it is different from the D-FF schematic in textbooks, the logic is the same and the number of transistors is small.
The transfer gate acts as a switch and turns on or off depending on the state value of the clock "C".
There is a loop circuit (latch circuit) using two inverters in the first and second stages, where data is held.
In operation, when clock "C" is low (Low/0), the signal of data "D" is read, and when clock "C" is up (rising) next, the data is output to output "Q". The data is output to output "Q".
Figure 1-1 General D-FF Circuit Structure
Figure 1-2 shows the circuit structure of a typical D-FF when "C" is low (Low/0).
The signal of "D" is stored in the inverter loop of the first stage, and the data of the previous cycle is held in the inverter loop of the second stage.
The transfer gate connecting the first and second inverter loops is off, so no signal is transmitted.
Figure 1-2 "C" is Low (0)
Figure 1-3 shows the state when "C" is "H" (High/1).
When "C" is up, the data stored in the inverter loop in the previous stage is transmitted to the subsequent stage.
Figure 1-3: When "C" is Low (0)
When "C" is set to ↑, no signal comes in from "D" as shown in Figure 1-3.
At this time, if the signal has not completed one round of the inverter loop in the previous stage, the signal fluctuates between "L" and "H" and becomes an intermediate potential (metastable). Of course, since this is a CMOS circuit, the signal will go "L" or "H" after a certain time, but since the metastable state is longer than the delay time, data may be missed.
This is why the setup time is limited.
Also, if "D" changes just before the input of "D" closes with "C" up, data that should have been captured in the next cycle is captured earlier. In the same way, oscillation or metastable may occur in the inverter loop, so the "D" signal must remain stable for a while after "C" goes up.
For this reason, there is a hold time constraint.
Therefore, when there is only one clock, there is no problem as long as the setup and hold time time constraints are observed. However, when there are multiple clocks, you need to be careful.
That's all for this issue. In the next issue, we will discuss metastable.
Asynchronous Clocks and Verification Techniques Next