How to switch FPGA configuration data HDL version [#3/3].

In this issue, we will discuss [#3], a method for creating an HDL design (state machine circuit) to control the FPGA to automatically switch between multiple configuration data stored in EPCQ/EPCQA/EPCS , which has been introduced in [#1] and [#2].

Please refer to the following article for the previous contents.

How to Switch FPGA Configuration Data in HDL [#1/3]

How to Switch FPGA Configuration Data in HDL [#2/3]

Image of switching configuration data (this time's specification)

Step 2: Create a design for Page 1

Create and compile the design for application1_image (stored in Page 1), which is the transition destination of factory_image, and generate the sof file.

Page 1 in the configuration ROM

Switch the Project Navigator window to the Files view and select application1_image.v from the list. Right-click > Set as Top-Level Entity and change the project's top-level hierarchical module to application1_image.

Change the top-level hierarchical module of the project to application1_image

Open the application1_image.v file and make the following modifications

Change the bus width of data_in in the remote_update module to 24bit

This time, we are working on three top-level hierarchical modules, factory_image, application1_image, and application2_image, while sharing the project (*). This means that the pin layout constraints are common. Therefore, start Pin Planner and set the Reserved Pin option for the following pins that are assigned to pins in this project but not used in the application1_image design. The setting value should be selected according to the evaluation board used. The following is based on the Beryll board.

Set the Reserved term of dip_sw to as input tri-stated
Set the Reserved term of led[3] as output driving vcc

All Pins List in Pin Planner for application1_image (an example when using Beryll board)

Execute Processing menu > Start Compilation to compile application1_image. Perform timing verification to confirm that the required specifications are met. Then, rename the generated top.sof file as app1_image.sof.

Write app1_image.sof to the FPGA with the Programmer and verify the operation.

Now you have built the configuration data 1 to be written to Page 1 of the configuration ROM!

[Hanako's Tweet #3: Project Configuration].

Since factory_image and application1_image or application2_image are different designs, we usually prepare and work on Quartus® Prime projects for each of them, but in this sample project, Page 0 and Page 1 are the same. However, this sample project has the same input/output pin configuration (pin names, layout, etc.) for both Page 0 and Page 1 designs, even though they have different operating specifications, so they can share the same project constraints (options).

Therefore, in this sample, instead of creating individual projects, only the top-level hierarchical modules are re-set within the same project while compiling and generating programming files (*.sof). If you wish to switch configuration data using Altera Remote Update IP in your own work, please create a separate project for each Page according to the specifications of the board and the application to be operated.

Step 3: Create a design for Page 2

Create a design for application2_image (stored on Page 2), another transition destination of factory_image, compile it, verify it on the actual device, and rename the sof file.

We will leave it up to you to decide how you want application2_image to behave, but in order to make it return to the Page 0 image (i.e., reconfigure it) while application2_image is running, we need to set reconfig = 1 to Altera Remote Update IP to issue reconfig = 1. (* Refer to application1_image.v)

After creating a design, add it to the project by selecting "Project" menu > Add/Remove Files in Project.

Transition image of each design's operation specifications and configuration data (after modification)

This time, I remade application1_image.v a little and changed the lighting specification of L-tika, and created application2_image.v.

For example, it looks like this. (See the figure below.)
(* I just changed the led[2:0] lighting pattern of application1_image.v.)

Remake example

Switch the Project Navigator window to the Files view and select application2_image.v from the list.
Right-click > Set as Top-Level Entity and change the top-level hierarchical module of the project to application2_image.

Change the top-level hierarchical module of the project to application2_image

Execute Processing menu > Start Compilation to compile application2_image.

Perform timing verification to confirm that the required specifications are met.

Then, rename the generated top.sof file as app2_image.sof.

Write app1_image.sof to the FPGA with the Programmer and verify the operation.

Now you have built the configuration data 2 to be written to Page 2 of the configuration ROM!

Step 4: Create a programming file for the configuration ROM

Create a programming file for the target configuration ROM by mixing the three configuration data.

Select File menu > Convert Programming Files to activate the dialog box.
In the Output programming file section, set the contents of the file to be generated.

[A] Programming file type: Select the format of the programming file for the configuration ROM according to the connection configuration of the board to be used (.pof or .jic)
[B] Configuration device: Programming the Configuration ROM
[C] Mode: Select the mode according to the connection configuration of the board to be used
[D] File name: Specify the folder and file name for the programming file to be generated

The evaluation board Beryll used this time has a JTAG Indirect Configuration programming specification for the configuration ROM, so set as follows.

[A] Programming file type: JTAG Indirect Configuration File (.jic)
[B] Configuration device: EPCS128
[C] Mode: Active Serial
[D] File name: output_ file/remote_update.jic (* Folder path and file name are free.)

Output programming file setting (Convert Programming Files dialog box)

For the Create Memory Map File option, see [Hanako's Tweet #5] on the same page.

Next, in Input files to convert, set the Flash Loader and the SOF file of the original data. (* If the format to be generated is .pof, there is no Flash Loader line.)
After selecting the Flash Loader line, click the Add Device button and select the FPGA model number.

Select the model number of the FPGA on which to build the Flash Loader (Convert Programming Files dialog box)

Click the Add Sof Page button to add the SOF Data row. (Figure i below) This time, we will prepare three pages.

Next, select the SOF Data line of Page_0, click the Add file button (Figure ii below), and set the factory_image.sof to be stored.

Prepare Page 0, Page 1, and Page 2 (Convert Programming Files dialog box)

Select the SOF Data line of Page_0 and click the Properties button (Figure iii below). （Select the SOF Data row of Page_0 and click the Properties button (Figure iii below).

Set the properties of Page 0 (Convert Programming Files dialog box)

In the SOF Data properties dialog box, specify the Start address of Page 0.

Address mode for selected pages : Start
Start address : 0x00000000

If you also want to specify the End address, set Address mode to Block and enter the Start address and End address.

SOF Data Properties dialog box

[Hanako's Comments #4: Compression of sof files]

Each sof file set in "SOF Data" can be compressed to generate a programming file. Select a file name and click the Properties button. (Figure iii+α below) If necessary, activate the Compression option in the Properties screen.

Compression options for sof files

Similarly, set app1_image.sof to Page_1 and app2_image.sof to Page_2, and set the Start address defined in factory_image.v.

Click the Generate button, and when the message "Successfully" is displayed, the file generation is complete!

Generate Convert Files (Convert Programming Files Dowalog Box)

About Memory Address Map File] [Hanako's Tweet #5.

When the Create Memory map File option is enabled and a programming file is generated, a memory address map file (.map) is also generated at the same time. map file can be opened in a text editor.

The map file can be opened in a text editor. It contains the start and end addresses of the data on each page as specified when the programming file was created.

The figure below shows the map file when only the start address is specified (Address mode for selected pages: Start). In this case, the END ADDRESS shows the end address of the address used for the stored data.

.map file

Step 5: Execute programming to the configuration ROM

Check the orientation of the DIP switches on the Beryll board beforehand so that application1_image is selected as the initial image transition destination.

DIP switch on the Beryll board (application1_image is selected)

Start the Programmer (Tools menu), make the necessary settings (Hardware Setup, Mode selection, set programming files, etc.), and then click the Start button to execute programming.

Programmer window

Step 6: Verify operation on the actual device

The Beryll board has nCONFIG, nSTATUS, CONF_DONE, and INIT_DONE pins pulled up via resistors, and LEDs are also connected to the board, so the configuration status is easily visible. We will check the operation there as well.

A schematic of the Beryll board is available at
Beryll - Cyclone® V GX Basic Board

Power on the Beryll board!
At first, the factory_image stored on Page 0 runs.

Then, when the reconfiguration command to the Altera Remote Update IP is reached, the LEDs connected to the user I/O will turn off, and the LEDs connected to CONF_DONE and INIT_CONF will also turn off once.

The LEDs connected to CONF_DONE and INIT_CONF will also turn off at the same time. The LEDs of CONF_DONE and INIT_CONF will automatically reconfigure and turn on again, confirming that the application1_image stored in Page 1 has been moved to operation.

When application1_image runs and reaches the reconfiguration instruction to the Altera Remote Update IP, the CONF_DONE, INIT_CONF, and User I/O LEDs turn off as before, and reconfiguration is automatically performed, The LEDs of CONF_DONE and INIT_CONF turn on again, and it can be confirmed that the transition to factory_image has been made.

Now, change the direction of the DIP switch to change the transition destination to application2_image.

DIP switch of Beryll (application2_image is selected)

When the reconfiguration instruction to Altera Remote Update IP arrives, you can confirm that the transition is made to factory_image When the reconfiguration instruction to Altera Remote Update IP arrives, the transition to factory_image can be confirmed.

Operation status on the actual machine

It is done! Success!

This time, since the operation was as simple as L-tickering, no error state was generated and the LED indicating an error did not light up.

In addition, the LED indicating State 6 was lit at the same time as the reconfiguration command to Altera Remote Update, so it was not at a level that could be seen and could not be photographed, but we were able to confirm that the specified image operation was performed according to the state of the DIP switch.

Finally

As you can see, by incorporating and controlling the Altera Remote Update IP using the sample design as a reference, you can easily configure a specification to switch the configuration data.
We hope you will try it, too.