How to switch FPGA configuration data HDL version [#1/3].

Hello, my name is Intel F. Hanako.

My name is Intel F. Hanako and I am a technical support engineer for Intel® FPGA products at Macnica.

In this article, I would like to introduce how to create an HDL design (state machine circuit) to control the FPGA to automatically switch multiple configuration data stored in EPCQ/EPCQA/EPCS.

Configuration Data Switching Image

An FPGA operates only when it receives configuration data from an external source.

In order to have the FPGA receive and send configuration data on the board, it is necessary to implement a ROM that stores the data.
There are various configuration schemes depending on the FPGA family used and the ROM used, but the simplest method is Active Serial (AS) configuration using Intel® FPGA-specific configuration ROMs (EPCQ, EPCQA, EPCS). Serial) configuration using Intel® FPGA-specific configuration ROMs (EPCQ, EPCQA, and EPCS).

[Reference]
Corresponding table of configuration schemes supported by each family of FPGAs

Normally, one configuration data for the opposing FPGA is stored in EPCQ, EPCQA, or EPCS, but multiple configurations can be stored. Using the EPCQ/EPCQA/EPCS area in this way has the following advantages.

- Free space in EPCQ/EPCQA/EPCS can be used effectively.
- It eliminates the need to write separate configuration images for each board, reducing man-hours.
- FPGA operation can be switched according to board status.

This specification is commonly referred to by the manufacturer as the "remote system update feature.

This article is a simplified version of the basic operation flow of Quartus® Prime, so please refer to the various documents on the following pages if necessary.
Altera® FPGA Development Flow

Target Device Families

FPGA: Cyclone® V, Cyclone® IV, Arria® V, Arria® II, Startix® V, Stratix® IV
- Configuration ROM: EPCQ, EPCQA, EPCS

Configuration data switching specifications

After power-on, the target FPGA first configures the data stored in Page0 (starting address position 0x000000) of the EPCQ/EPCQA/EPCS. Then, if necessary, it accesses the data stored on another page and reconfigures it.
If the configuration fails, the FPGA automatically recovers by configuring the data on Page0.

Configuration data switching image

Note that the target FPGA cannot switch between configuration data other than the configuration data stored in Page 0. For example, to switch from the application with configuration data 1 to the application with configuration data n, it is necessary to switch once to the application with configuration data 0 on Page 0.

To have the FPGA perform this configuration data switching operation, use the Altera Remote Update IP. This IP is a free function and is also available in Quartus Prime Lite Edition.

[Reference]
Altera Remote Update IP Core User Guide

FPGA and evaluation board used in this project

Any board with the target FPGA and configuration ROM can be used. For this project, we will be using a Mpression Beryll board with Cyclone V (5CGXFC4C6F27C7) and EPCS128.

Beryll - Cyclone® V GX Basic Board

Download Sample Designs

From this point on, we will use a sample design for simplified explanation.
The sample designs are available from the Design Store operated by Intel® PSG (Programmable Solutions Division).

[How to Get Sample Designs]
Get FPGA Sample Designs for Free!

[Sample Designs to Download]
Remote System Upgrade (RSU) Design Example (for Cyclone V SoC Development Kit)

This example design is designed for the Cyclone® V SoC. The parameters of each IP (AlteraPLL, Altera Remote Update) included in the design are also configured for Cyclone® V. If this project is used for another family, it is recommended to re-create the IP.

[For users who want to use the project as default].

In this article, the sample design has been slightly modified and explained so that it can be used with FPGAs and configuration ROMs other than the target device of the sample design.

If you would like to use the example design (compatible with the Cyclone® V SoC Development Kit) as is, please see the document "Remote System Upgrade Design Example User Guide" available on the example design page of the Design Store. Remote System Upgrade Design Example User Guide" available on the sample designs page of the Design Store.

Set up the sample design project in Quartus® Prime

Extract the par file downloaded from the Design Store. Please refer to the TIPS below to learn how to extract the file.

How to extract the FPGA sample design .par file:
(Hanako-style extraction, described in the latter part of this article, is easy.)

Extracting the .par file

Overview of the sample design

Run Analysis & Elaboration to get an overview of the sample design.

After that, look at the Project Navigator and you will see that CV_pll and remote_update exist under the factory_image module. An overview of each module is shown below.

Project Navigator window

The source folder in the project's working folder contains factory_image.v, currently set as the top-level hierarchical module, and application_image.v, another top-level hierarchical module of configuration data. The sources of each are shown below.

Looking at each source, we can see that the configuration is structured to switch between storing the factory_image data in Page 0 of the configuration ROM and storing the application_image data in Page 1.

The following figure shows the operational specifications of the sample design.

For more details, please refer to the document "Remote System Upgrade Design Example User Guide" available on the sample design page of the Design Store.

Operation Specifications and Configuration Data Transition Images for Each Design

The factory_image.v consists of a state machine that controls the Altera Remote Update IP (remote_update) to migrate to application_image.v. The flow is shown in the above figure. The flow in this case is the 7 steps from State 0 to State 6 in the above figure, with a state indicating an error in State 7.

State 0 (set reset = 1 to reset Altera Remote Update IP)

→ State 1 (reset is canceled)

→ State 2 (Empty state)

→ State 3 (set AnF = 1 before loading the application image)

→ State 4 (set the starting address of the application image to be transitioned)

→ State 5 (disable watchdog timer)

→ State 6 (set reconfig= 1 to start the application image)

AnF in State 3 stands for Application not Factory, and the AnF bit must be set to 1'b1 before reconfiguration triggers for the application image. The starting address of the memory where the application image data is stored is then specified.

To set the AnF bit, have the user logic issue param = 3'b101, data_in = 24'h000001 and write_param = 1'b1 to the Altera Remote Update IP.

The application_image.v is configured to flash LEDs[2:0] simultaneously for 7 seconds and jump to the Page 0 configuration image.

The LEDs in each design are shown in the figure below.

LED lighting design for each design
State # (LED [2..0]) (LED [2..0])	Functions	LED State # (LED [2..0]) LEDs	LED 3 LED 2	LED 2 LED 1	LED 1 LED 1 LED 2 LED 3	Image Status
State 0 (3'b000)	reset =1, reset RSU IP					factory_Image
State 1 (3'b001)	release reset
State 2 (3'b010)	empty state
State 3 (3'b011)	AnF=1
State 4 (3'b100)	Set application_image start address
State 5 (3'b101)	disable watchdog
State 6 (3'b110)	reconfig=1, boot application Image					application_image
State 6 (3'b110)	LED[2...0] blink for 7 seconds					application_image
State 7 (default)	Hold					Error

Blink LED blinks / light LED on / light LED off

Sample Project Switching Specifications Changed

In the sample, the configuration data for 5CSXFC6D6ES (Cyclone® V) is stored in EPCQ256 with two images.

The evaluation board Beryll is equipped with 5CGXFC4C6F27C7 and EPCS128. 5CGXFC4C6F27C7 configuration data is an uncompressed Raw binary file (.rbf) with a size of 33,958,560 bits. EPCS128 has a capacity of 134,217,728 bits.

Excerpt from each datasheet

[Reference materials].

Cyclone® V Device Datasheet (see Configuration Specifications > Configuration Files)

Serial Configuration (EPCS) Devices Datasheet

This means that three uncompressed configuration data can be stored. In this case, the configuration ROM in the sample project will be changed as shown in the figure below.

Change the configuration of the configuration ROM in the sample project

To apply this configuration, rename the existing application_image.v file to application1_image.v and edit the module name from application_image to application1_image .

In addition, add the source/application1_image.v file and delete the source/application_image.v file in the Project menu > Add/Remove Files in Project.

You will also create your own original design for the new Configuration Data 2 later.

Work flow from now on

We will work in the following 6 steps.

Step 1: Create a design for Page 0

Step 2: Create design for Page 1

Step 3: Create the design for Page 2

Step 4: Create a programming file for the configuration ROM

Step 5: Execute programming to the configuration ROM

Step 6: Verify operation on the actual device

Now let's start with Step 1.
Create a design to write to Page 0, compile, verify on the actual device, and rename the sof file. (Continue to #2 below)

How to switch FPGA configuration data HDL version [#2/3].