How to switch FPGA configuration data HDL version [#2/3].

This is part [#2] of a series of articles following [#1] on how to create an HDL design (state machine circuit) that allows the FPGA to automatically switch between multiple configuration data stored in the EPCQ/EPCQA/EPCS.

Please refer to the following article for the previous contents.

How to Switch FPGA Configuration Data in HDL [#1/3].

Image of switching configuration data (specification of this time)

Step 1: Create a design for Page 0

Create a design for writing to Page 0, compile it, verify it on the actual device, and rename the sof file.

Confirm that the top-level design of the sample project currently set in the Project Navigator window is factory_image.

The design to be stored in Page 0 of the configuration ROM is factory_image (image)

1. edit the sample project settings according to the evaluation board

We will use a Beryll board from Mpression with a Cyclone® V (5CGXFC4C6F27C7) and an EPCS128.
The sample design project is configured for the Cyclone® V SoC Development Kit (5CSXFC6D6F31C6N with EPCQ256), so we will make some modifications to the constraint settings to make it compatible with the Beryll board.

1-1. change the device model number

In the Assignments menu > Device, change the device model number to 5CGXFC4C6F27C7. In this case, you will be asked if you want to delete the pin layout information. Since the evaluation board is different this time and the pin layout is also changed, select "Yes" (delete the assignment information).

Device dialog box

1-2. Configuration Mode Settings

Click the Device and Pin Options button in the Device dialog box, select Configuration scheme in the Configuration category, and specify Remote as the Configuration mode. For the EPCS128 used in this case, select Active Serial x1 (can use configuration Device) for Configuration scheme.

There is no need to set the Configuration device field. The programming file required in this case is created separately with the Convert Programming Files function, since it mixes multiple configuration data.

Configuration category (Device and Pin Option dialog box)

Other options such as Unused Pins and Voltage category should be changed according to the specifications of the evaluation board to be used. 2.

Edit the sample design

This project consists of three files: two IP cores (CV_pll, remote_update) and the top level hierarchy (factory_image) (see figure below). Edit each design file to adapt it to the configuration of the evaluation board and configuration ROM used in this project.

2-1. change the parameters of the PLL circuit (CV_pll)

In the Project Navigator window, double-click the CV_pll module to display the Parameter Settings window.

Launch the Altera PLL IP parameter setting window.

On the evaluation board, enter the frequency of the clock input from the oscillator to the FPGA in the Reference Clock Frequency field. In the case of the Beryll board used this time, four oscillators with different frequencies are connected to the FPGA.
Leave the output clock frequency of the PLL at 40 MHz to match the sample.

Click the Finish button to update the design. Even if there are no changes to the parameters, use the Finish button to update the design file so that it applies to the version of Quartus® Prime you are using.
When the Generation Successful message is displayed, click the Exit button to close the window.

Altera PLL IP Parameter Setting Screen

2-2. update Altera Remote Update IP (remote_update)

The Altera Remote Update IP used in the sample project is an old-style IP called "ALTREMOTE_UPDATE megafunction. You can update the parameters of ALTREMOTE_UPDATE to use it, but this time we will update it to the new Altera Remote Update IP (for use in new projects in the future).
In other words, this time we will create an Altera Remote Update IP with the same name as the existing ALTREMOTE_UPDATE and overwrite it.

From the Tools menu > IP Catalog, search for Altera Remote Update and double-click on it.
In the New IP Variation window, specify the name of the IP to be created and the path to the folder where it will be saved. In this case, enter remote_update as the Entity name to replace the existing remote_update.v.

Launch Altera Remote Update IP from IP Catalog

In the "Which configuration device will you be using?" field, specify the configuration ROM to be used on the evaluation board. This time, select EPCS128.
At the same time, enable (On) the Add Support for writing configuration parameters option.

Altera Remote Update IP Parameter Setting Screen

In the Generate dialog box that appears after clicking the Generate HDL button, select Verilog as the language in the Synthesis section. (Quartus® Prime supports mixed languages, so there is no problem even if you generate in VHDL.)

Leave the Path in the Output Directory section as the default.
Click the Generate button to generate the design file. When file generation is complete, click the Finish button to close the window.

Generation screen for Altera Remote Update IP

Now, organize your working folder and Quartus® Prime settings so that there are no conflicts between the existing remote_update file and the remote_update file you just created.

Open the working folder in Explorer and locate the file named remote_update. (This does not include the remote_update folder in the working folder.)

Delete all remote_update files except the .qsys and .sopcinfo files.

Organize the files in the working folder

Then select Project menu > Add/Remove Files in Project in Quartus® Prime.
First, delete the existing remote_update.qip (remote_update.v).

Delete a design file (Settings dialog box > Files category)

Next, click the Browse button to the right of the File name field and select remote_update.qip in the Working folder > Remote_update folder > Synthesis folder in order to register the newly generated remote_update. Select remote_update.qip in the synthesis folder.

Add a design file (Settings dialog box > Files category)

Close the Settings window with the OK button.

2-3 Edit the control circuit for the Altera Remote Update IP

In order to adapt the sample design to this specification, edit the factory_image.v file stored on Page 0.
There are three editing points!

Point 1: Change the starting address of each image to be stored in the configuration ROM to match this specification.

Point 2: Modify the bus width of the data connected to the Altera Remote Update IP because the configuration ROM is different from the sample.

Point 3: Add an action to select a configuration image to transition to.

Below is an example of these three edits.

[Point 1] Change the starting address of each image stored in the configuration ROM to match the current specifications.

Change the start address of the configuration ROM, which contains the configuration data that transitions from the Page 0 image, for the Beryll board.

The uncompressed raw binary file (.rbf) size of the configuration data for the 5CGXFC4C6F27C7 (Cyclone® V) used this time is 33,958,560 bits. Therefore, the factory_image configuration data (uncompressed) uses EPCS128 sectors 0-16 (H'000000 to H'43FFFF). Similarly, the configuration data for application1_image and application2_image can be converted as shown in the figure (1) below.

Next, rename the parameter name in the parameter declaration in the second line to APP1_IMAGE_START for application1_image, and add APP2_IMAGE_START as the parameter declaration for application2_image in the third line, as shown in Figure 2 below. START as the parameter declaration for application2_image.

In addition, edit each parameter value to the start address of each Page. Since EPCS128 is used this time, change the address width from 32 bits to 24 bits. (* To change the data input data_in of Altera Remote Update to 24 bits, which is the assignment destination, after this.)

Change point 1

[Ref]
EPCS Devices
Serial Configuration (EPCS) Devices Datasheet
EPCQ Devices
Quad-Serial Configuration (EPCQ) Devices Datasheet
EPCQA Devices
EPCQ-A Serial Configuration Device Datasheet

[Point 2] Modify the bus width of the data connected to the Altera Remote Update IP

The data input data_in and data output data_out of the Altera Remote Update IP (remote_update) are 24 bits when using EPCS128 because of the 3-byte addressing mode. (In the sample project, the target was EPCQ256, so it was 32 bits in 4-byte addressing mode.)

Change the bus width of data_in and data_out in the reg and wire declarations to 24 bits as shown in the figures (3) and (4) below.

Changes in point 2

For an easy way to check the data bus width, see [Hanako's Tweet, Part 2] on the same page.

[Point 3] Add an action to select a configuration image to transition to

This time, the DIP switches on the Beryll board are used to determine whether to transition from factory_image to application1_image or application2_image.

DIP switches on the Beryll board

For this purpose, an input pin is added. (See Figure 5)

Modification of point 3 (1)

Also, add conditional statements for transitions. For example, like this. (See Figure 6 below)
(* When dip_sw is 0, data_in is assigned APP1_IMAGE_START (i.e. 24'h440000) and when dip_sw is 1, data_in is assigned APP2_IMAGE_START (i.e. 24'h880000))

Changes in point 3 (2)

2-4. change pin layout

Change the pin layout in Pin Planner according to the evaluation board and the edited design. At the same time, change the I/O standard according to the board. The following is an example of using a Beryll board. (In the case of this example, the input pins have been added, so Analysis & Elaboration should be run beforehand.)

Pin Planner's All Pins List for factory_image (example using Beryll board)

Execute compilation and rename the sof file.

Execute "Processing" menu > "Start Compilation" to compile factory_image.

Compilation execution

Perform timing verification to confirm that the required specifications are met.
After that, rename the generated top.sof file as factory_image.sof. Write factory_image.sof to FPGA with
Programmer and check the operation.

[Hanako's tweet Part 2. How to check the data width of Altera Remote Update IP].

It is a bit troublesome to check the bit width of data input data_in and data output data_out of Altera Remote Update IP from Datasheet of the reference material I introduced earlier. In such cases, here is an easy way to check them.

When you create an Altera Remote Update IP in the IP Catalog, you specify the configuration ROM to be used in the "Which configuration device will you be using? If you select View menu > Block Symbol, an image diagram will be displayed. Check the bus width of the data_in and data_out.

Check the data width of Altera Remote Update IP

Next, build the transition destination design.

Now we have built the configuration data 0 to be written to Page 0 of the configuration ROM!

Next, let's create the configuration data to be written to Page 1 and Page 2. (Continue to #3 below)

How to switch FPGA configuration data in HDL [#3/3].