The purpose of this content is to organize and provide designers with an in-depth understanding of the correct design techniques and knowledge of FPGAs and CPLDs so that they will find Intel's devices easy to use and highly reliable, while at the same time reducing the instability factor in the design within the device as much as possible.
While it is important to learn the basics of key design techniques and implement them in devices in order to build reliable (i.e., working) systems in FPGA and CPLD development, it is also important to understand the operating characteristics of FPGAs and CPLDs as a preliminary knowledge. However, it is also important to understand the operating characteristics of FPGAs and CPLDs as a preliminary knowledge.
The main factors that can prevent FPGAs and CPLDs from operating properly are: - Voltage fluctuations
- Voltage fluctuations
- Ambient temperature
- Lot variations, process evolution
These external factors are extremely common factors, and as they fluctuate, the timing (delay) of the FPGA or CPLD will also fluctuate. For example, the higher the voltage and the lower the temperature, the smaller the delay and the faster the operation. Many malfunctions are caused by this timing variation. For example, "I replaced the device and it worked. "It worked when I cooled the device down. These are almost always caused by timing problems. These are almost always caused by timing problems. Here is a problem that you may not be aware of. In the short term, it may be due to variations in the device lot, and in the long term, it may be due to changes in delay values caused by process evolution.
On the other hand, FPGA and CPLD delay values are defined under at least two operating conditions, the fastest (Fast) and the slowest (Slow) (three conditions for FPGAs at 65 nm process and below, and four conditions for FPGAs at 28 nm process and below), and development software is required to have as many operating The development software has as many libraries (timing models) as the number of operating conditions. Even if a device changes lots or processes, the device will still be a good device as long as the defined fastest and worst timing models are not violated.
If you do not understand these facts well in advance before designing a device, you will be hurt unexpectedly. No matter how good the device manufacturer claims the device is, if the system does not work, it will be useless. Therefore, let us summarize the concept of "good products" (as defined in the specifications) shipped from device manufacturers.
Production lot
Generally, each device is available in several speed grades. For example, there are 6, 7, and 8 speed grades. These speed grades have separate timing models, but slower devices may contain faster devices. In other words, a device with a speed grade of 8 may also contain the performance of a speed grade of 7. In other words, a speed grade 8 device may have the performance of a speed grade 7 and a speed grade 8 device, which means that ambiguities in FPGA and CPLD design can sometimes cause malfunctions due to timing variations.
Process Change
When a process change is made, the same timing model is used as in the previous product, as well as the production lot issue. However, the delay values tend to increase with the process change. As a result, when the new process is used, there is a tendency to get "noisy and stuck," "glitchy," or "noisy and stuck. Glitching. or "ground bounce causes the counter to malfunction. The result is that the newer process products tend to be faster.
Timing Models
Intel recommends the following operating conditions
- Operating voltage range (V)
- Ambient temperature range (T)
- Lot-to-lot variation (including process changes) (P)
A development software timing model is provided under these PVT conditions. The timing models used for timing verification (timing analysis using TimeQuest or timing simulation using EDA simulator tools) of Intel FPGAs/CPLDs are the Fast model for the fastest operating conditions and the Slow model for the slowest operating conditions. However, it is not sufficient to analyze all paths in a circuit using only the worst-case values of the fastest and slowest models. Lot variations must also be considered. This is because a device in which only one part of the circuit runs slightly faster due to lot variation may have tighter timing than a device in which all parts of the circuit run at their slowest. This analysis is called Minimum/Maximum analysis, and Quartus® Prime takes these factors into account.
The results calculated by Quartus® Prime are the values that meet the user's design requirements for clock-synchronous design. For example, the operating frequency (Fmax) in the Slow model from TimeQuest represents the lowest operating frequency for the slowest path of the device, so a system operating at or below that frequency is guaranteed. In the same way, ensuring that the calculated setup/hold time value on the system will allow it to operate under Intel's recommended conditions.
For these reasons, when using Intel FPGAs or CPLDs, it is recommended that detailed verification of operation by timing analysis be performed after compilation (place and route) is complete.
This is the preliminary knowledge for FPGA/CPLD design.
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