1. Introduction
This content introduces how to Boot Nios® II from Flash ROM (Quad SPI Flash) with Boot Copier or XIP (Execute in Place) using the Generic Serial Flash Interface Altera® FPGA IP (GSFI).
For more information on GSFI, please refer to the following contents.
Reference: Generic Serial Flash Interface IP User Guide
Reference: Embedded Peripherals IP - Generic Serial Flash Interface Sample
For the difference between XIP and Boot Copier, please refer to the following contents.
Reference: Configuration of Nios® II Boot and settings for each Boot Option
2. Overview
There is no significant change in "Relationship between Boot and Flash Controller" and "Basic Concept of Boot Configuration" described in the following contents.
Reference: Embedded Peripherals IP - Comparison of Various Flash Controllers > 3. Relationship with Nios® II Boot - (In Japanese)
Reference: Nios® II Boot Option ~ EPCQ Flash ~ (using AS IF)
Reference: Nios® II Boot Option ~ QSPI Flash ~ (using User I/O IF)
However, by changing the Flash Controller to GSFI, the following two points should be noted.
- GSFI parameters must be set according to I/O Mode (Standard/QUAD) and Flash ROM specifications.
- Since mem_init of Nios® II SBT is not supported, it is necessary to generate a HEX file by command.
These two points are included in the explanation.
The configuration of Platform Designer used in this explanation is shown in Figure 1.
[Figure 1] Platform Designer Configuration Example
3. Other IP and settings required for Quartus® Prime
3-1. Other IP Parameter Settings
In Platform Designer, the settings required for Nios® II and other IPs other than GSFI are the same as before.
Please also refer to the following contents.
Reference: Nios® II Boot Option ~ EPCQ Flash ~ (using AS IF)
Reference: Nios® II Boot Option ~ QSPI Flash ~ (using User I/O IF)
The Reset Vector Offset setting in the Nios® II Processor parameter setting determines to which address in the Flash ROM the Nios® II software is stored.
When storing in Configuration ROM (using AS Interface), refer to the following information to make the setting.
When storing in Flash ROM connected to User I/O, freely set the address you wish to store.
Reference: Nios® II Boot Option ~ EPCQ Flash ~ (using AS IF) > How to set Reset Vector offset
3-2. Quartus® Prime Settings
When storing the Nios® II software in the Configuration ROM, it is necessary to match the parameter settings of GSFI with the configuration scheme settings of Quartus® Prime.
Open Assignments tab -> Device -> Device and Pin Options -> Configuration and set the items shown in Figure 2.
- In the case of Standard Boot, set Active Serial x 1 (can use Configuration Device).
- In case of Quad Boot, Active Serial x 4 (can use Configuration Device)
[Figure 2] Device and Pin Options for Quartus® Prime
When a JIC or POF file is written to the Configuration ROM, the value of Dummy cycles written to the Nonvolatile Configuration Register changes depending on the combination of Flash ROM capacity and AS x 1 / AS x 4.
When using the AS (Active Serial) Interface, if the GSFI parameter settings and the Configuration scheme settings do not match, it will not be possible to boot correctly. Refer to the following information to check the value of Dummy cycles and adjust the GSFI parameters.
Reference: Supported Third Party Configuration Devices
When using the User I/O Interface, the Nonvolatile Configuration Register is not rewritten. If necessary, rewrite or adjust GSFI parameters.
You can check the Nonvolatile Configuration Register with the memory test of the sample software below.
Reference: Embedded Peripherals IP - Generic Serial Flash Interface Memory Test Samples
4. Setting parameters of Generic Serial Flash Interface
In Platform Designer, GSFI parameter settings are usually hidden by the Show/Hide Hidden Parameters setting. Figure 3 shows the default GSFI register settings.
By setting the Default Settings item, the initial values can be set after IP startup. Set the Default Settings item so that Nios® II can boot after power-on.
Refer to the contents below to confirm the contents of the registers and how to display the parameter settings.
Reference: Embedded Peripherals IP - Generic Serial Flash Interface Memory Test Samples
[Figure 3] Default Settings of GSFI Default Settings
4-1. AS Interface and User I/O Interface Settings
Both AS (Active Serial) Interface and User I/O are supported for connection to the GSFI Flash ROM.
For the AS Interface, the default settings are fine. The Tool automatically connects to the AS Interface without the need to explicitly connect to the FPGA external PIN.
For User I/O, enable the "Disable dedicated Active Serial interface" and "Enable SPI pins interface" settings as shown in Figure 4. Export the signals connected to the Flash ROM and connect them directly to the FPGA external PINs that connect to the Flash ROM. Do not forget to write the timing constraint file (SDC file).
Reference: Quartus® Beginner's Guide - Timing Constraint Method
[Figure 4] GSFI User I/O Settings
4-2. Addressing and Clock Baudrate Settings
The Addressing setting is made in the Control Register. The settings differ depending on the size of the capacity.
The Flash ROM access frequency (DCLK) is set by the Clock Baudrate Register. It sets how much to divide from the GSFI operating frequency, which can be configured from 1/2 to 1/32 of the operating frequency.
[Table 1] Examples of Addressing and Clock Baudrate Settings
| Register Name | Default Value | Setting Example |
| Control Register | 0x00000001 |
128 or less (3-byte addressing): 0x00000001 256 or more (4-byte addressing): 0x00000101 |
| Clock Boudrate Register | 0x00000010 |
1/2 of operating frequency : 0x00000001 1/32 of operating frequency : 0x00000010 |
4-3. Standard (x1) Settings
The I/O Mode setting is made in the Protocol Settings Register. When I/O mode is set to Standard, use the default settings.
The Read opcode is set in the Read Instruction Register. The settings differ depending on the I/O Mode and Flash ROM model number. The following is an example of the settings for EPCQ256.
[Table 2] I/O Mode and Read opcode settings for Standard (x1)
| Register Name | Default Value | Setting Example of EPCQ256 |
| Protocol Settings Register | 0x00000000 | OK with default setting |
| Read Instruction Register | 0x00000003 |
Set according to Flash ROM specifications [12:8] : Dummy cycles : 0x0 [7:0] : Read opcode : 0x03 |
4-4. QUAD (x4) Settings
The I/O Mode setting is made in the Protocol Settings Register. When I/O Mode is set to QUAD, change the Read Data and Read Address settings in the Protocol Settings Register to Quad (0x2).
The Read opcode is set in the Read Instruction Register. The settings differ depending on the I/O Mode and Flash ROM model number. The following is an example of the settings for the EPCQ256.
[Table 3] I/O Mode and Read opcode settings for QUAD (x4)
| Register Name | Default Value | Setting Example of EPCQ256 |
| Protocol Settings Register | 0x00000000 |
0x00022000 [17:16] : Read Data out transfer mode : 0x2 [13:12] : Read Address transfer mode : 0x2 |
| Read Instruction Register | 0x00000003 |
Set according to Flash ROM specifications. [12:8] : Dummy cycles : 0xA (0x6 for EPCQA) [7:0] : Read opcode : 0xEB |
4-5. [Reference] Read Instruction Code List
Table 4 shows examples of Read Instruction Register settings for each Flash ROM for reference.
Note:
This table is compiled based on the contents described in the User's Guide, so please check the Flash ROM specifications again and verify them.
[Table 4] Read Instruction Code List
| Flash ROM Name (*1) |
Vender | Standard | QUAD | ||
| Read opcode | Dummy cycles | Read opcode |
Dummy cycles (*2) |
||
| EPCQ64 | Altera® | 0x03 | 0x0 | 0xEB | 0xC |
| EPCQ256 | Altera® | 0x03 | 0x0 | 0xEB | 0xA |
| EPCQA128 | Altera® | 0x03 | 0x0 | 0xEB | 0x6 |
| N25Q64A | Micron | 0x03 | 0x0 | 0xEB | 0xC |
| MT25QL256 | Micron | 0x03 | 0x0 | 0xEB | 0xA |
| MX25L256 | Macronix | 0x03 | 0x0 | 0xEC | 0x6 |
| IS25LP256 | ISSI | 0x03 | 0x0 | 0xEC | 0xC |
Note:
*1: Please obtain the User Guide for Third Party Flash ROM from the respective vendor.
*2: Depending on the value of the Nonvolatile Configuration Register register, Dummy cycles may need to be adjusted separately (see 3-2. Quartus® Prime Settings ).
5. Setting of Nios® II SBT
After completing the settings up to chapter 4, run "Generate HDL" in Platform Designer to generate a SOPCINFO file. Also compile in Quartus® Prime to generate an SOF file.
Using that SOPCINFO file, generate a Project in Nios® II SBT, change the BSP settings and run Build to generate an ELF file (executable file).
Point:
- When verifying Boot, use simple software such as Hello World or just turning on LEDs, instead of the software used in production, to reduce the possibility of Boot failure due to the software description.
- The Boot status can be output to UART Core (or JTAG UART). As shown in Fig. 5,
BSP Editor -> Main tab -> Advanced -> hal -> log_port : value is set to UART Core (or JTAG UART), the log of Boot will be output. You can check "how far the process has progressed" and "whether the main function has been called" on the Terminal.
By entering a value in BSP Editor -> Main tab -> Advanced -> hal -> log_flags : value, the number of logs displayed will be increased. (Figure 5 shows log_flags = 0).
[Figure 5] Boot Log Port Settings
5-1. Nios® II Settings When Booting with Boot Copier
Boot Copier is a method in which all Linker Sections are set to RAM (On Chip RAM or external RAM) and Nios® II is operated by extracting necessary data from Flash ROM to RAM using Boot Loader called Boot Copier.
Since the Boot Loader expands all the data, all hal.linker settings should be turned off.
Figure 6 shows an example.
Note:
Figure 6 shows an example of the following settings in the Vectors tab of the Nios® II parameters.
- Reset vector memory: GSFI
- Exception vector memory: On Chip RAM or external RAM
For more details, please refer to the following contents.
[Figure 6] Nios® II SBT BSP Editor Settings in Boot Copier
5-2. Nios® II Settings When Booting with XIP
XIP (Execute in Place) is a method of running Nios® II on Flash ROM by allocating the .text area of the Linker Section to Flash Controller.
If you have set the settings to store sections other than .text in RAM, you need to enable the alt_load setting in order to expand them into RAM at Boot time.
Figure 7 shows an example of this setting.
In the case of the Linker Section setting shown in Figure 7, all hal.linker settings should be turned ON.
Note:
Figure 7 shows an example of the following settings in the Vectors tab of the Nios® II parameters.
- Reset vector memory: GSFI
- Exception vector memory: On Chip RAM or external RAM
If the Exception vector memory is also set to GSFI, turn off "enable_alt_load_copy_exceptions" in the alt_load setting. For details, please refer to the following contents.
[Figure 7] Nios® II SBT BSP Editor Settings in XIP
6. How to generate Programming File
In case of Nios® II Boot using GSFI, since mem_init is not supported, the HEX file to be stored in Flash ROM is generated by command in Nios® II Command Shell.
The command to be executed differs depending on Boot Copier and XIP.
6-1. ELF to HEX command for Boot Copier
The procedure to generate HEX file for Boot Copier is described below. After confirming that the Nios® II software runs with Run As, generate the HEX file.
-
Copy boot_loader_cfi.srec to the Application folder of the Nios® II SBT from the following path:
C:\intelFPGA\20.1\nios2eds\components\altera_nios2\boot_loader_cfi.srecPoint: The above paths are based on ver 20.1 as an example, so please change the paths according to your version.
In Nios® II SBT, right-click on the Application folder and select Nios® II -> Nios® II Command Shell.
Execute the alt-file-convert.exe command with the appropriate arguments for your environment. An example of the command is shown below.
alt-file-convert.exe -I elf32-littlenios2 -O hex --input=Boot_LED_Check.elf --output=GSFI_BOOT.hex --base=0x02000000 --end=0x03ffffff --reset=0x02420000 --out-data-width=8 --boot=boot_loader_cfi.srec<Explanation of command arguments>
alt-file-convert.exe -I elf32-littlenios2 -O hex --input=<ELF File Name> --output=<HEX File Name> --base=<GSFI BASE Address> --end=<GSFI END Address> --reset=<Reset Vector> --out-data-width=8 --boot=boot_loader_cfi.srec
- GSFI BASE Address and GSFI END Address are the values set in Platform Designer.
- Reset Vector = GSFI BASE Address + Reset Vector Offset is the value set by the Nios® II parameter.
6-2. ELF to HEX Command for XIP
This section describes the procedure for generating a HEX file for XIP. Please change to the Boot Copier setting, confirm that the Nios® II software runs with Run As, and then change back to the XIP setting to generate the HEX file.
For debugging XIP, please refer to the information below.
Reference: How to debug in XIP configuration - (In Japanese)
-
In the Nios® II SBT, right-click on the Application folder and select Nios® II -> Nios® II Command Shell.
Execute the elf2hex.exe command with the appropriate arguments for your environment. An example of the command is shown below.
elf2hex.exe Boot_LED_Check.elf 0x02000000 0x03ffffff --width=8 --little-endian-mem --create-lanes=0 GSFI_BOOT_XIP.hex<Explanation of command arguments>
elf2hex.exe <ELF File Name> <GSFI BASE Address> <GSFI END Address> --width=8 --little-endian-mem --create-lanes=0 <HEX File Name>
- GSFI BASE Address and GSFI END Address are the values set in Platform Designer.
6-3. How to generate JIC / POF file
Generate JIC / POF file by Convert Programming File.
When storing in the AS Interface Configuration ROM, the JIC file can be generated and written via JTAG using the Quartus® Prime Programmer.
When storing in Flash ROM connected to the User I/O Interface, a POF file can be generated and written via JTAG using a design with a built-in PFL (Parallel Flash Loader) and Quartus® Prime Programmer.
In addition, by enabling Create config data RPD in the Convert Programming File, a JIC / POF binary file can be generated at the same time.
Please refer to the following contents when generating JIC files.
Reference: Nios® II Boot Option ~ EPCQ Flash ~ (using AS IF) > 4-2. Generating the JIC File
To generate POF file, please refer to the following contents including PFL.
Reference: Nios® II Boot Option ~ QSPI Flash ~ (using User I/O IF) > 4-2. Generation of POF file
Point:
In case of XIP, Absolute addressing may not work well depending on the HEX file settings.
In this case, please refer to the FAQ below.
Reference: How do I adjust the HEX storage address for Relative Addressing in Convert Programming Files? - (In Japanese)
We have prepared a "Nios® II Summary Page - (In Japanese)" that summarizes various information on Nios® II. Please refer to this page as well, as it is full of useful information other than this article.