1. Introduction
Platform Designer has many types of Flash Controllers that access Flash ROM, and the latest IP is the Generic Serial Flash Interface IP (GSFI).
Reference: Generic Serial Flash Interface IP User Guide
For more information on other Flash Controllers, please click here.
Reference: Embedded Peripherals IP - Flash Controller Sample
Reference: Embedded Peripherals IP - Flash Controller Comparison
The new Flash Controller has greatly expanded its functionality from the previous Flash Controller. The Avalon Slave Port can be accessed to change the SCLK (Flash ROM access frequency) frequency and I/O Mode (QUAD or Standard) to support various types of Flash ROM.
On the other hand, it is necessary to create a master processing sequence that manipulates registers according to the specifications of the Flash ROM used.
The sample software in this article is based on the Nios® II software, and it is compatible with Flash ROMs from a variety of vendors.
GSFI has sample software available from the manufacturer, and we have prepared our own Memory Test sample software based on it.
Note:
The sample software described in this article is not guaranteed to work, and should be customized and verified according to the specifications of the Flash ROM to be used.
2. register map
Table 1 provides an overview of GSFI's register map. Refer to the User's Guide for the latest details.
Reference: Generic Serial Flash Interface IP User Guide
Table 1. GSFI Register Map Summary
| Offset | Register Name | R/W Description | Description |
| 0x0 | Control Register | R/W |
Sets Addressing mode, Chip Select, and GSFI IP Enable. [7:4] : Selects the flash device [0] : IP Enable |
| 0x1 | SPI Clock Baud-rate Register | R/W |
Sets the SPI Clock (SCLK) Baud-rate. [4:0] : Baud rate divisor |
| 0x2 | CS Delay Setting Register | R/W |
Adjusts the nCS operation timing. [11:8]: tSHSL [7:4]: CS de-assert [3:0]: CS assert |
| 0x3 | Read Capturing Register | R/W |
Delays the read data logic by the value of IP_CLK cycles. [3:0]: Read delay |
| 0x4 | Operating Protocols Setting Register | R/W |
Sets I/O Mode for Instruction, Read, and Write commands. [17:16] : Read Data out transfer mode [13:12] : Read Address transfer mode [9:8] : Write Data in transfer mode [5:4] : Write Address transfer mode [1:0] : Instruction transfer mode - 0x0: Standard SPI mode - communicates using DQ0 |
| 0x5 | Read Instruction Register | R/W |
Sets the command to be issued when Read is issued to the Avalon MEM Port. [12:8] : Dummy cycles [7:0] : Read opcode - The command to be set changes depending on the IO Mode. |
| 0x6 | Write Instruction Register | R/W |
Sets the command to be issued when Write is issued to the Avalon MEM Port. [15:8] : Polling opcode - Sets the command for Status Register. [7:0] : Write opcode - The command to be set changes depending on the IO Mode. |
| 0x7 | Flash Command Setting Register | R/W |
Sets the command to be issued. [20:16] : Number of dummy cycles - Sets the dummy cycle value. [15:12] : Number of data bytes - Set 0x0 for commands that do not require data. [11] : Data type - Indicates whether the number of data bytes set in [15:12] is Read or Write. [10:8] : Number of address bytes - Sets 3/4 bytes addressing. [7:0] : Opcode |
| 0x8 | Flash Command Control Register | W | Executes the command set in the Offset 0x7 register. |
| 0x9 | Flash Command Address Register | R/W Offset | Offset Sets the address value to be assigned to the command set in the 0x7 register. |
| 0xA | Flash Command Write Data 0 Register | R/W Offset | Offset Sets the Write Data (lower 4 bytes) assigned to the command set by the register 0x7. |
| 0xB | Flash Command Write Data 1 Register | R/W Offset | Sets the Write Data (upper 4 bytes) assigned to the command set by the register Offset 0x7. |
| 0xC | Flash Command Read Data 0 Register | 0 Register R | Offset Stores the Read Data (lower 4 bytes) returned after executing the register 0x8. |
| 0xD | Flash Command Read Data 1 Register | Register R | Offset The register of 0x8 is executed and the returned Read Data (upper 4 bytes) is stored. 3. |
About Platform Designer's Hidden Parameter
The initial values of the registers shown in Table 1 can be set using the IP parameter of Platform Designer.
Although normally hidden, the initial values can be set by right-clicking on the IP name and selecting "Show/Hide Hidden Parameters" as shown in Figure 1.
The register can be set in the software, but it can also be set here.
You can also use the Nios II Boot, the default values must be set according to Flash ROM because GSFI performs the Boot process before the user software is booted.
Reference: Nios® II Boot Option ~ Boot method using Generic Serial Flash Interface
Figure 1. GSFI Parameter Setting Hidden Parameter
4. sample design overview
The following is an overview of the sample design presented in this article.
Kit used: Cycloen V GX Starter Development Kit
(Qsys files and software can be ported to other kits for reproduction)Tool Version: Quartus ® Prime ver20.1_Standard
Main IP used: Nios® II, On-Chip RAM, JTAG UART, PIO (LED), GSFI
Nios II/f (Gen2): Instruction/data cache: 4 KB
On-Chip RAM: 128 KB (work memory)
Approximate software capacity: program size (code + initialized data):
enable_small_c_library [enabled] 28 KBytes, [disabled] 80 KBytes
Note RAM is small in relation to software capacity:
If the RAM capacity is small compared to the software capacity, a stack overflow may occur.
Figure 2 shows a connection diagram of Platform Designer.
Figure 2. Platform Designer Connection Diagram
4-1. Sample Software Description
This sample software has GSFI control functions and is designed to access various Flash ROMs by changing the #define statement settings according to the Flash ROM specifications.
Write errors caused by software processing, such as Protect Sector being applied, Write Enable not being issued, or WIP check not being performed, are unlikely to occur, so Flash ROM can be accessed with minimal software modification and Memory Test can be performed on all areas. Therefore, the Flash ROM can be accessed with minimal software modification, and a Memory Test can be performed on the entire area.
With the default settings, the software performs the following operations on the EPCQ256 connected to the AS Interface as the Configuration ROM.
- Release Protect Sector
- Execute Erase for 1 sector and verify if the data is 0xFF.
- Writes data from 0x0000_0000 in Flash ROM for each sub-sector, and rewrites data for one sector.
- Perform Verify for each sub-sector.
- When a verify error occurs, the read data is displayed and the error data can be confirmed.
Note: If a Verify error occurs, the read data is displayed and the error data can be checked. Flash area that must not be rewritten:
Do not execute the program on Flash ROM that has areas that should not be rewritten.
Table 2 shows an overview of the sample software in this article.
Table 2. Summary of Sample Software
| Software Name | Overview |
| GSFI_Access_Sample.c | Main process is described. |
| GSFI_Operation_sample.h | Contains Flash ROM command information and GSFI register information. |
| GSFI_Operation_sample.c | GSFI_Operation_sample.c describes functions to control GSFI. |
For details of the implemented functions, see the attached source code.
By changing the constants defined in the #define statement below, you can use the software according to your own Platform Designer configuration.
#define statements found in GSFI_Access_Sample.c
/***********************************************************************************
* re- definitions
* * This section redefines the constants defined in "system.h" for use in
* this source file.
* Please change the constants on the right side with reference to "system.h" when you use it.
***********************************************************************************/
#define SFC_AVL_CSR_BASE (INTEL_GENERIC_SERIAL_ FLASH_INTERFACE_TOP_0_AVL_CSR_BASE)
#define SFC_AVL_CSR_SPAN (INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_SPAN)
#define SFC_AVL_ MEM_BASE (INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_BASE)
#define SFC_AVL_MEM_SPAN (INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_SPAN 0_AVL_MEM_SPAN)
By changing the constants defined in the #define statement below, you can change the Sector area to be written, IO Mode, and Protect Sector settings.
The #define statements described in GSFI_Access_Sample.c
/***********************************************************************************
* definitions (define)
* * This source code in default state rewrites data for one sector from 0x0000_00000 in Flash ROM.
* Please try with Flash ROM that can be rewritten without any problem.
* By changing the values of SEC_BASE_ADD and NUM_OF_SEC defined in the #define statement, the sector to be rewritten can be adjusted.
* If the value set is not the base address of the Sector or the number of Sectors exceeds the Flash ROM, Nois II will exit.
***********************************************************************************/
#define SEC_BASE_ADD (0x00000000) // Base address for Erase and Write and Read
#define NUM_OF_SEC (1) // Number of sectors to Erase and Write and Read
#define IO_MODE (0) // 0:Standard, 1:Dual, 2:QUAD
#define CLOCK_RATE (0x1) // IP default is 0x10 (f[Hz]/32). 0x1(f[Hz]/2) ~ 0x10(f[Hz]/32) can be set.
#define SECTOR_LOOK (0x0) // Sector lock setting. 0x0 releases the lock.
#define DATA_LENGTH (0x00001000) // Data size Default is Sub Sector size 0x00001000
#define WRITE_DATA (0x00) // Write Data
#define PRINT_COLUMNS (16) // Number of columns to print with Print_Data() 1~256
Various Flash ROMs can be supported by changing the constants defined in the #define statement below.
Note Macronix Flash ROMs are used:
When using Macronix Flash ROM, set MACRONIX_ISSI to 1.
When using ISSI Flash ROM, set MACRONIX_ISSI and ADDRESS_IO_MODE to 1.
When using EPCQA, set ADDRESS_IO_MODE to 1.
The #define statement found in GSFI_Operation_sample.h
/***********************************************************************************
* definitions (define)
* Change the settings according to the type of Flash ROM.
* *********************************************************************************/
#define MACRONIX_ISSI (0) // Macronix and ISSI Flash ROM requires Addressing setting and QUAD setting, so set it to 1 when used.
#define ADDRESS_IO_MODE (0) // Set to 1 if Address I/O Mode for QUAD Write must be set to Standard. (Enable for ISSI and EPCQA)
/*******************************************************************************
* Flash ROM Command Info based on EPCQ256 EPCQA128 MT25QL 256 MX25L25645G IS25LP256D
*******************************************************************************/
#define READ_DEVICE_ID_CMD ( 0x9F)
#define READ_DEVICE_ID_BYTES (4)
#define READ_STATUS_CMD (0x05)
#define READ_STATUS_BYTES (1)
#define READ_FLAG_STATUS_CMD (0x70) // EPCQA Macronix ISSI is not supported
#define READ_FLAG_STATUS_BYTES (1)
#define READ_NON_VOLA_CONFIG_CMD (0xB5) // EPCQA is not supported. EPCQ Micron:0xB5, Macronix:0x15, ISSI:0x61
#define READ_NON_VOLA_CONFIG_BYTES (2)
#define WRITE_STATUS_CMD (0x01)
#define WRITE_STATUS_BYTES (1)
#define WRITE_ NON_VOLA_CONFIG_CMD (0xB1) // EPCQA Macronix ISSI is not supported
#define WRITE_NON_VOLA_CONFIG_BYTES (2)
#define WRITE_ENABLE_CMD (0x06)
WRITE_ENABLE_BYTES (0)
#define WRITE_DISABLE_CMD (0x04)
#define WRITE_DISABLE_BYTES (0)
#define READ_BYTES_CMD (0x03)
#define READ_BYTES_DUMMY (0)
#define EXTENDED_DUAL_FAST_READ_CMD (0xBB)
#define EXTENDED_DUAL_FAST_READ_DUMMY (10) // EPCQ Micron:8 or 10 or 12, EPCQA ISSI Macronix:6 or 10
# define EXTENDED_QUAD_FAST_READ_CMD (0xEB)
#define EXTENDED_QUAD_FAST_READ_DUMMY (10) // EPCQ Micron:8 or 10 or 12, EPCQA ISSI Macronix:6 or 10
# define WRITE_BYTES_CMD (0x02)
#define WRITE_BYTES_DUMMY (0)
#define EXTENDED_DUAL_FAST_WRITE_CMD (0xD2) // EPCQA Macronix ISSI is not supported
# define EXTENDED_DUAL_FAST_WRITE_DUMMY (0)
#define EXTENDED_QUAD_FAST_WRITE_CMD (0x12) //EPCQ:0x12, EPCQA:0x32, Micron Macronix ISSI:0x38
# define EXTENDED_QUAD_FAST_WRITE_DUMMY (0)
#define ERASE_SUBSECTOR_CMD (0x20)
#define ERASE_SUBSECTOR_DUMMY (0)
#define ERASE_SECTOR_CMD (0xD8 )
#define ERASE_SECTOR_DUMMY (0)
#define ERASE_BULK_CMD (0xC7)
#define ERASE_BULK_DUMMY (0)
/*********************************************** ********************************
*Flash ROM Command Info for Macronix ISSI base on MX25L25645G IS25LP256D
* *********************************** *****************************************/
#define ENABLE_4BYTE_FOR_MX25L_CMD (0xB7)
#define ENABLE_4BYTE_FOR_MX25L_BYTES (0)
DISABLE_4BYTE_FOR_MX25L_CMD (0xE9) // Macronix:0xE9, ISSI:0x29
#define DISABLE_4BYTE_FOR_MX25L_BYTES (0)
/******************************** ***********************************************
* Flash ROM Command Info Other Registers base on MT25QL256
* ********************************* *******************************************/
#define READ_VOLA_CONFIG_CMD (0x85)
#define READ_VOLA_CONFIG_BYTES (1)
#define READ_ENHAN_ VOLA_CONFIG_CMD (0x65)
#define READ_ENHAN_VOLA_CONFIG_BYTES (1)
#define READ_EXTEN_ADD_REG_CMD (0xC8)
#define READ_EXTEN_ADD_REG_BYTES (1)
# define READ_GEN_PURPOSE_REG_CMD (0x96)
#define READ_GEN_PURPOSE_REG_BYTES (1)
#define READ_SEC_PROTECT_CMD (0x2D)
#define READ_SEC_PROTECT_ BYTES (1)
#define READ_VOLA_LOCK_BIT_CMD (0xE8)
#define READ_VOLA_LOCK_BIT_BYTES (1)
#define READ_NON_VOLA_LOCK_BIT_CMD (0xE2)
#define READ_VOLA_LOCK_BIT_CMD (0xE2) VOLA_LOCK_BIT_BYTES (1)
#define READ_GLOBAL_FREEZE_BIT_CMD (0xA7)
#define READ_GLOBAL_FREEZE_BIT_BYTES (1)
4-2. Results of Sample Software Operation Checks
Table 3 lists the Flash ROMs that were verified to work with the sample software software in this article. The modifications made during the verification are listed in the "#define statement modifications" section of the table, and should be modified according to the type of Flash ROM used.
Note:
Table 3 is described as an "example" based on the results of operation verification in our environment. Please customize it as necessary.
Table 3. List of Flash ROMs that have been tested with the sample software
| Vender | Flash ROM (*1) | IO Mode | #define statement modification (*2) |
| Altera® | EPCQ64 | Standard DUAL QUAD | <GSFI_Operation_sample.h> |
| Altera® | EPCQA128 | Standard QUAD |
Dual Write Not Support <GSFI_Operation_sample.h> |
| Altera® | EPCQ256 | Standard DUAL QUAD | OK by default |
| Micron | MT25QL128 | Standard DUAL QUAD | <GSFI_Operation_sample.h> EXTENDED_DUAL_FAST_READ_DUMMY (10 or 12) EXTENDED_QUAD_FAST_READ_DUMMY (10 or 12) EXTENDED_QUAD_FAST_WRITE_ CMD (0x38) |
| Micron | MT25QL256 | Standard DUAL QUAD | <GSFI_Operation_sample.h> EXTENDED_DUAL_FAST_READ_DUMMY (10) EXTENDED_QUAD_FAST_READ_DUMMY (10) EXTENDED_QUAD_FAST_WRITE_CMD (0x38 ) |
| Macronix | MX25L256 | Standard QUAD |
Dual Write Not Support <GSFI_Operation_sample.h> |
| ISSI | IS25LP128 | Standard QUAD |
Dual Write Not Support <GSFI_Operation_sample.h> |
| ISSI | IS25LP256 | Standard QUAD |
Dual Write Not Support <GSFI_Operation_sample.h> |
Notes:
*1 Please obtain the User Guide for Third Party Flash ROMs from the respective vendor.
*2 The value of Dummy Cycles changes depending on the value of Nonvolatile Configuration Register of each Flash ROM; check the value by Memory Test and set EXTENDED_QUAD_FAST_READ_DUMMY and EXTENDED_DUAL_FAST_READ_DUMMY to 0x41. FAST_READ_DUMMY settings. Especially when using as Configuration ROM, the value of Nonvolatile Configuration Register is rewritten by writing JIC / POF. Please refer to the following information regarding the value to be rewritten.
Reference: Supported Third Party Configuration Devices
4-3. Sample Software Verification Procedure
Nios® II SBT to create and validate a sample software project. The same procedure is used when verifying with user-created Qsys.
Minimum System Requirements
- Nios® II Processor Core (Fast or Economy)
- Generic Serial Flash Interface
- Execution RAM (On Chip RAM (approx. 40k Bytes or more) or external RAM)
- Implementation of stdout function (e.g., JTAG UART or UART Core, to display results in a Printf statement)
Steps
- Generate sopcinfo file by Generate HDL in Platform Designer.
- Nios® II SBT to generate Nios II Application and BSP from Template at
(Template can be hello_world_small or hello_world etc.) - Replace software with sample software and modify #define statement (*3)
- Set BSP Editor to run On Chip RAM or external RAM and run Generate BSP ( for reference )
- Run Build and Run AS
Note: *3 After Build is executed, modify #define statement:
*If #define statement is modified again after Build is executed, the changes may not be reflected.
4-4. sample software operation
Nios® II SBT, the work RAM (On Chip RAM in this design) will be used to run Nios® II is executed in the Work RAM (On Chip RAM in this design).
Nios® II Console displays the Status Register information of the Flash ROM, the value of the set sector base address, and the number of sectors to be written. The Nios® II Console then sets the GSFI settings, updates the Protect Sector, displays the GSFI register information, and starts Erase Write Read.
The log for one sector of EPCQ 256 is shown below.
Hello from Nios II!
Source File: GSFI_Access_Sample.c
Open flash device.
Device ID = 0x1019ba20
Read Status = 0x0
Read Flag Status = 0x81
READ NONVOLATILE CONFIGURATION REGISTER = 0xafee
READ VOLATILE CONFIGURATION REGISTER = 0xfb
READ ENHANCED VOLATILE CONFIGURATION REGISTER = 0xdf
READ EXTENDED ADDRESS REGISTER = 0x0
READ GENERAL PURPOSE READ REGISTER = 0x0
READ SECTOR PROTECTION = 0x0
READ VOLATILE LOCK BITS = 0x0
READ NONVOLATILE LOCK BITS = 0x0
READ GLOBAL FREEZE BIT = 0x0
The Start Sector Address you set = 0x00000000
The Number of Sector you set = 1
There are no setting errors.
Set Clock Rate [fHz]/2.
Protect Change OK.
Set IO Mode 0(0:Standard, 1:Dual, 2:QUAD)
Read Status = 0x0
Read Flag Status = 0x81
READ NONVOLATILE CONFIGURATION REGISTER = 0 xafee
READ VOLATILE CONFIGURATION REGISTER = 0xfb
READ ENHANCED VOLATILE CONFIGURATION REGISTER = 0xdf
READ EXTENDED ADDRESS REGISTER = 0x0
READ GENERAL PURPOSE READ REGISTER = 0x0
READ SECTOR PROTECTION = 0x0
READ VOLATILE LOCK BITS = 0x0
READ NONVOLATILE LOCK BITS = 0x0
READ GLOBAL FREEZE BIT = 0x0
Print GSFI Register.
Offset 0x0 : 0x00000101
Offset 0x1 : 0x00000001
Offset 0x2 : 0x00000000
Offset 0x3 : 0x00000000
Offset 0x4 : 0x00000000
Offset 0x5 : 0x 00000003
Offset 0x6 : 0x00000502
Offset 0x7 : 0x000018a7
Offset 0x8 : 0x00000000
Offset 0x9 : 0x00000000
Offset 0xa : 0x00000000
Offset 0xb : 0x00000000
Offset 0xc : 0x00000000
Offset 0xd : 0x00000000
*******************************************
Number of Executions = 1 [n]
Erase/Write/Read Sector BASE Address = 0x00000000 (Sector Number = 0)
Start Erase.
Erase Sector Address = 0x00000000
Verify Address = 0x00000000 : Erase Verify was successful.
Verify Address = 0x00001000 : Erase Verify was successful.
Verify Address = 0x00002000 : Erase Verify was successful.
Verify Address = 0x00003000 : Erase
Verify Address = 0x00004000 : Erase Verify was successful.
Verify Address = 0x00005000 : Erase Verify was successful.
Verify Verify Address = 0x00006000 : Erase Verify was successful.
Verify Address = 0x00007000 : Erase Verify was successful.
Verify Address = 0x00008000 : Erase Verify
Verify Address = 0x00009000 : Erase Verify was successful.
Verify Address = 0x0000a000 : Erase Verify was successful.
Verify Address = 0x0000b000 : Erase Verify was successful. 0000b000 : Erase Verify was successful.
Verify Address = 0x0000c000 : Erase Verify was successful.
Verify Address = 0x0000d000 : Erase Verify was
Verify Address = 0x0000e000 : Erase Verify was successful.
Verify Address = 0x0000f000 : Erase Verify was successful.
End Erase.
Start Write Read Verify
Read Address 0x00000000 : Verify was successful.
Read Address 0x00001000 : Verify was successful.
Read Address 0x00002000 : Verify was
Read Address 0x00003000 : Verify was successful.
Read Address 0x00004000 : Verify was successful.
Read Address 0x00005000 : Verify was successful.
Read Address 0x00006000 : Verify was successful.
Read Address 0x00007000 : Verify was successful.
Read Address 0x00008000 : Verify was successful.
Read Address 0x00009000 : Verify was successful.
Read Address 0x0000a000 : Verify was successful.
Read Address 0x0000b000 : Verify was
Read Address 0x0000c000 : Verify was successful.
Read Address 0x0000d000 : Verify was successful.
Read Address 0x0000e000 : Verify was successful. successful.
Read Address 0x0000f000 : Verify was successful.
-Address--|00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f| ASCII
----------+--+--+--+--+--+-- +--+--+--+--+--+--+--+--+--+--+--+--+ ----------------
0x0000f000 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ................
0x000f0010 to 0x0000ffe0 are omitted (00 to FF are repeated)
0x0000fff0 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF ............... .
End Write Read Verify
Read Status = 0x0
Read Flag Status = 0x81
READ NONVOLATILE CONFIGURATION REGISTER = 0xafee
READ VOLATILE CONFIGURATION REGISTER = 0 xfb
READ ENHANCED VOLATILE CONFIGURATION REGISTER = 0xdf
READ EXTENDED ADDRESS REGISTER = 0x0
READ GENERAL PURPOSE READ REGISTER = 0x0
READ SECTOR PROTECTION = 0x0
READ VOLATILE LOCK BITS = 0x0
READ NONVOLATILE LOCK BITS = 0x0
READ GLOBAL FREEZE BIT = 0x0
****************** *************************
Free buf_read_data.
Free buf_write_data.
Free flash_info.
Finish Nios II.
****************** *************************