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Simulation with ADC in MAX® 10

Simulation with ADC in MAX® 10

  • Updated

1. Introduction

The design sample attached to this article is a sample that can be used as a starting point for simulation using the ADC in MAX 10. 
The documentation accompanying this article provides step-by-step instructions for simulation procedures using the published design samples. 
The materials explain the following

  • The environment in which the sample is used
  • Advantages of using this sample
  • Operation procedures of the simulation
  • Consistency with desk calculations -- Appendix 1 --
  • About the attached spreadsheet -- Appendix 2 --

The spreadsheet attached to this article is an Excel file for more effective verification by simulation. It is introduced in Appendix 2 in the latter half of the document. 2.

 

2. advantages of using this sample

The design sample and spreadsheet are attached to this article. 
The advantages of using the design sample are as follows

  • The objective can be reached relatively early, since there is no need to design from scratch by hand.
  • The samples can be used as a reference and applied to the design.

The advantages of using spreadsheets are described below.

  • Analog values can be converted into a format for simulation
    Test data can be easily created by simply pasting into a text file.
  • Calculate digital data
    Calculate expected values when considering the validity of simulation results.
  • Sample analog values
    In the absence of known values, you can tentatively use automatically generated values with random numbers. 
    Other than random numbers, a composite Sin wave can also be used. 3.

 

3. environment for use

The following development tools are used in this article.

Table 1  Development tools used in this article

Item No. Item Description
1 Quartus® Prime Development Software Standard Edition (hereafter referred to as Quartus® Prime) A tool for developing FPGA hardware. This document uses Quartus® Prime Development Software Standard Edition v18.1.
2 Modular ADC core IP This IP core can be used to control the ADC embedded in MAX® 10 FPGAs. In this document, it will be referred to as ADC IP core.
3 ModelSim® FPGA Starter Edition ModelSim® is a simulation tool that verifies the behavior of each signal by simulating waveforms to check the operation of logic circuits implemented in FPGAs. In this document, since Quartus® Prime v18.1 is used, the corresponding ModelSim® FPGA Starter Edition 10.5b is used.
4 Platform Designer 
(formerly Qsys) 		In FPGA hardware, it can be connected mainly to the internal bus Avalon-MM interface, etc., and incorporates each component ( Nios® II Processor, DMA Controller, Timer, PIO, On-Chip Memory, etc.) defined in the address map. It is a tool for users to build their own memory-mapped systems by incorporating components defined in the address map (Nios® II Processor, DMA Controller, Timer, PIO, On-Chip Memory, etc.).

 

Documents/Samples

____.png Documentation
📦 S ample Projects
📦 S preadsheet

 

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