＜エラーメッセージ＞
Error (170084): Can't route signal "xxxx~input" to atom "xxxx~output"
REFCLK から clock control blocks へ接続する事はできません。
（参考）Cyclone IV Device Handbook, Volume 2
https://www.intel.com.au/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-5v2.pdf
（Input Reference Clocking の Notes to Figure 1–26:）
（抜粋）
(2)"The REFCLK[1..0] and REFCLK[5..4] pins are dual-purpose differential REFCLK or DIFFCLK pins that reside in
banks 3B and 8B respectively. These clock input pins do not have access to the clock control blocks and GCLK
networks. For more details, refer to the Clock Networks and PLLs in Cyclone IV Devices chapter."
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カテゴリ：仕様
ツール：Quartus® Prime
デバイス：Cyclone® IV