Verilog HDL : Difference between blocking and non-blocking logic synthesis

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Hello, my name is Masuo.
I would like to talk about a time when I stumbled upon Verilog HDL syntax.

I was confused because there are two different ways to write the assignment of values in the example sentences that were shown during the training.
"a = b"
"a <= b"

Both mean "assign b to a".
I checked the literature to see what the difference is,

Blocking assignment (=): performed in sequential blocks, starting from the top
Non-blocking assignment (<=): Assignments can be made in sequential blocks regardless of the order in which the statements are written.

This is explained as follows.
A sequential block is the part of the always statement enclosed by begin and end.

The question was then asked, "What difference does it make to the actual synthesized circuit?" We used Quartus® II to verify the difference between blocking and non-blocking in a 4-input, 1-output circuit.

When we checked the results with RTL Viewer, we found that
blocking assignment generated various circuits depending on the order of description.
The non-blocking assignment generated the same circuit regardless of the order of the statements.

Blocking assignment (=)

always @ (posedge clk) begin 　dadb = da & db; 　dcdd = dc & dd; 　 dout = dadb & dcdd; end endmodule
always @ (posedge clk) begin 　dcdd = dc & dd; 　 dout = dadb & dcdd; 　dadb = da & db; end endmodule
always @ (posedge clk) begin 　 dout = dadb & dcdd; 　dadb = da & db; 　dcdd = dc & dd; end endmodule

Non-blocking assignment (<=)

always @ (posedge clk) begin 　dadb <= da & db; 　dcdd <= dc & dd; 　dout <= dadb & dcdd; end endmodule
always @ (posedge clk) begin 　dcdd <= dc & dd; 　dout <= dadb & dcdd; 　dadb <= da & db; end endmodule
always @ (posedge clk) begin 　dout <= dadb & dcdd; 　dadb <= da & db; 　dcdd <= dc & dd; end endmodule

What we learned

Blocking assignment in an always statement creates a circuit that depends on the order of execution, so if you don't understand the pairing of syntax description and logic synthesis, an unintended circuit will be created.

I often looked at example sentences and saw that they were written with blocking assignments (=) in assign statements and non-blocking assignments (<=) in always statements.
I wrote a blocking assignment in the always statement, which generated an unintended circuit and made me blush.

Verilog HDL : Difference between blocking and non-blocking logic synthesis