PLL in Altera® FPGAs (IP Generation Edition / PLL IP)

Hello, my name is Taro Washimiya. My name is Taro Washimiya and I am a technical support engineer for Altera® FPGA products at Macnica.

In "PLL in Altera® FPGAs", I explained the overview of PLL in FPGAs, and here I will explain the procedure to use PLL IP.

Please check which FPGA families can use the PLL IP in advance in "PLL in Altera® FPGAs".

1. generate PLL IP
2. connect to user circuit
3. check by simulation

Tools to be used

Quartus® Prime Standard Edition development software

Questa® - Altera® FPGA Edition

See Quartus® Prime Edition Comparison for the relationship between the target FPGA and development tool editions. If you have not yet installed the development software, you can obtain it from the Altera® FPGA website.

For more information, please refer to the following contents.

How to download Quartus® Prime Development Software and Questa® - Altera® FPGA Edition

How to install Quartus® Prime Development Software and Questa® - Altera® FPGA Edition

1. PLL IP Generation

This section uses a Cyclone® V project as an example.
Open a project where the target device is Cyclone® V or create a new project.
(For information on creating a Quartus® Prime project, see the Quartus® Getting Started Guide - How to Create a Project.)

In Quartus® Prime, type pll in the IP Catalog search bar.
You can then easily locate the PLL IP.
With the PLL IP highlighted, click Add.

Figure 1-1 Selecting PLL IP in IP Catalog

Specify the folder path where the PLL IP will be generated, a name for the PLL IP, and the language in which it will be generated (VHDL or Verilog) and click OK.
It is recommended that the IP be generated in the project's working folder or its subordinate folders.

Figure 1-2 Specifying the folder and name to generate the PLL IP

The PLL IP Configuration window will be launched.

Now, click on Documentation if you want to see detailed documentation and descriptions of each configuration item.

Figure 1-3 PLL IP Configuration Window

The following is a brief description of the main configuration items within each tab.

General Tab

General settings such as reference clock (input clock) frequency, locked pin enable/disable, number of output clocks, and output clock settings are made here.
As an example, the following settings are made here.

Item	Setting Value
Reference Clock Frequency (Input clock frequency)	50 (MHz)
Operation Mode	direct
Enable locked output port	Number Of Clocks
Number Of Clocks	Number Of Clocks On
outclk0 (output 0)
Desired Frequency (Output clock frequency)	100 (MHz)
Phase Shift (Phase shift value)	0 (ps)
Duty Cycle	50 (%)
outclk1 (Output 1)
Desired Frequency (Output clock frequency)	100 (MHz)
Phase Shift (Phase shift value)	90 (degrees)
Duty Cycle	50 (%)

Figure 1-4 PLL IP Configuration Window - General Tab

The following tabs provide an overview. For details on each item, please refer to the user guide by clicking on the link to the document introduced earlier.

Clock Switchover Tab

Some FPGA series support the ability to switch over with two inputs, and this tab is used to configure these settings.

Cascading tab

Cascading tab allows you to set the cascade connection of PLLs.

MIF Streaming Tab

Configures the Dynamic Phase Shift function using the MIF file that contains the PLL configuration data.

Note that Cyclone® V does not support this function.

Settings Tab

This tab allows you to set PLL auto-reset, PLL bandwidth preset, Dynamic Reconfiguration, Dynamic Phase Shift, and Dynamic Phase Alignment (DPA) settings.

Advanced Parameters Tab

Confirm PLL parameter names and values, such as PLL M/N/C counter values and VCO frequencies.

After completing the various settings, click Finish to generate the IP.

Figure 1-5 PLL IP generation completed

After confirming "Generation Successful," click Exit, and the window shown below will appear.
Click Yes to add the generated IP design to the currently opened project. (If you clicked No, please set up the addition manually.)

Figure 1-6 PLL IP related files are automatically added to the project

You have now completed the generation of the PLL IP.
Let's connect it to the user circuit you are designing and proceed with the logic design.

If you need to change the settings of the PLL IP, please refer to this FAQ.

FAQ] How to start the IP edit screen

After editing the necessary parameters, generate the PLL IP again. 2.

2) Connecting to the User Circuit

Once the PLL IP is generated, connect it to the user logic.

If you are not familiar with Verilog-HDL or VHDL, please refer to this page. See Calling Subordinate Modules (Blocks) in this page.

If you are designing with schematic (schematic), the symbols for the schematic editor are also generated when IP is generated, so please call the IP symbols created by the user in the schematic editor to connect.

However, Schematics cannot perform RTL simulation with 3rd party tool simulators. It is still recommended to design in HDL.

＜If you are not familiar with HDL description , try to use the conversion function from schematic to HLD in the schematic editor of Quartus® Prime.

Please refer to the document on the following page to learn how to convert.

Quartus® Beginner's Guide - Using the Schematic Editor

Once you have finished creating the upper-level design file, try synthesizing it by selecting Processing > Start > Start Analysis & Synthesis from the menu at
Quartus® Prime.
Did it complete successfully?

If you converted from a schematic, logic synthesis cannot be performed correctly if both the schematic file (BDF file) and the converted HDL file (V file for Verilog-HDL, VHDL file for VHDL) are registered in the project. (Delete unused design files from the Project menu > Add/Remove Files in Project.)

Confirmation by Simulation

Now, let's check the design by RTL simulation.
In this case, we will use Questa® Sim - Altera® FPGA Edition.
A testbench is required to check in simulation. The testbench is created by the user
For more information on how to write a testbench, please refer to this page.

Let's get started! Test Bench

Once you have a testbench, you are ready to run the simulation.
You can also manually manipulate Questa® Sim to run the simulation, but here is a convenient way. Please refer to it for reference.

Simulation using NativeLink functionality

Simulation using msel_setup.tcl

How to edit and use msim_setup.tcl

That's all for now, Taro Washimiya has introduced the steps from creation to simulation of PLL IP.

PLL in Altera® FPGAs (IP Generation Edition / PLL IP)

Contents