Introduction
Hello, my name is Totto. I'm Totto, and I'm feeling that memory is very deep every day.
Last time, I understood how DDR3 SDRAM works.
This time, I wondered how DDR3 SDRAM interfaces with FPGA, so I decided to investigate.
So, I decided to ask my senior engineer, Mr. Choucho, about it.
Totto : "How do FPGA and DDR3 SDRAM interface with FPGA?"
senior : "Well, try to create a memory interface with "MegaWizard Plug- In Manager" first!
Totto : "・・・・・"
At first, I decided to try to create a memory interface as I was told.
While generating the memory interface...
A question arose on the following screen.
There are two types of memory interfaces, UniPHY and ALTMEMPHY.
So I decided to ask my senior engineer, Mr. Choucho, about it.
Totto : "Which one should I choose, UniPHY or ALTMEMPHY?"
senior : "What kind of device do you use?"
Totto : "Cyclone ® V"
senior : "UniPHY then. What is UniPHY?"
Without knowing what UniPHY is, I managed to generate a memory interface.
Overview of memory interface
Totto : "If a controller controls memory, what is UniPHY? What is PHY anyway? What is PHY?"
What is PHY?
As shown in the image below, it is the part that receives the first electrical signal from the memory, USB, Internet cable, etc. connected to the controller.
The PHY chip physically receives the first electrical signal from USB, etc., and converts the electrical signal to digital data (1 , 0 ). (It also converts digital data to electrical signals.)
So, Altera's FPGA has a built-in PHY in the FPGA, and the part that first receives electrical signals from the memory (DDR3 in this column) is the UniPHY and ALTMEMPHY? I am convinced.
Summary of this article
- PHY is the part that first receives electrical signals from memory, USB, Internet cables, etc.
- The PHY converts electrical signals to digital data ( 1 , 0 ) and digital data ( 1 , 0 ) to electrical signals.
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