Introduction
Hello, my name is Totto. I am learning about memory day by day under the inspiration of my senior engineer, Mr. Choucho.
This time, I would like to write about the principle of memory operation.
Write ? Read?
I have been researching DDR3-SDRAM write and read operations. The following is the structure of DRAM.
A DRAM cell consists of one transistor and one capacitor.
(Note: The above diagram is an image.
Write
Write High
1 . High by increasing the voltage on the word lines and bit lines.
2 . By increasing the voltage of the bit line, current flows from the word line and charge accumulates in the capacitor.
Write Low
1 . Raise the voltage on the word line and set the bit line Low, which releases the charge from the capacitor and leaves no charge on the capacitor.
Read
Read High
1 . Set the word line high and the bit line low.
2 . Release the charge from the capacitor to raise the potential of the bit line and identify it as High.
Read Low
1 . The word line is set to High.
2 . Since there is no charge on the capacitor, no current flows and there is no change in the voltage of the bit line, which is determined to be Low.
Small talk
Totto : "What is the refresh operation?"
Senior : "What happens to a battery if it is left unattended?"
Totto : "It discharges naturally."
Senior : "Correct! Just like a cell phone battery, a capacitor gradually loses its charge and needs to be recharged. That is the refresh operation. "
The refresh operation retains data by recharging the cell's capacitors.
Now that I understood how memory devices work, I wondered how memory interfaces with FPGAs, so I decided to look into it.
Summary of this article
- Memory is a place where data is temporarily stored.
- A DRAM is made up of one transistor and one capacitor.
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