Introduction
This article describes the CAN (Controller Area Network) configuration of the Mpression Sulfur Type-A Development Kit (hereinafter referred to as "Sulfur") and the interface between the FPGA and the microcontroller with built-in CAN controller (MCU). This section also describes the verification of CAN I/F.In addition, sample designs (FPGA and MCU) prepared for CAN I/F verification and operation check procedures are also introduced.
The parts and block diagrams related to Sulfur's CAN I/F are shown below.
Figure 1. Sulfur Type-A CAN I/F related blocks
For detailed specifications, please refer to the documents ( Sulfur Type-A Kit User Manual Ver.1.1, etc.) that can be downloaded from the following page.
Since Agilex™ 5 E-Series (FPGA) is not CAN-compatible, it is configured to realize CAN interface by implementing a CAN-compatible MCU "NXP LPC54616".
Although it is possible to close the MCU for CAN communication, the sample design uses the SPI interface between the FPGA and the MCU to pass CAN send/receive data.
1. Equipment and development environment
This section describes the tools, versions, and development machine requirements (OS) necessary to run the design demo.
1-1. Equipment
The equipment required to run the sample design is as follows
- Sulfur Type-A Development Kit "Sulfur Type-A Development Kit " x1
- FPGA download cable " Intel® FPGA Download Cable II " x1
- MCU-Link Debug Probe," an MCU debugger connection cable x1
- CAN loopback cable (general-purpose cable; 120Ω CAN bus termination is included in Sulfur) x1
Point: The MCU debugger connection cable also includes a UART-USB converter IC, which can be used to connect to the MCU terminal in addition to the JTAG debugger connection. It is available at a relatively low cost.
Note: For the CAN loopback cable, we have verified that the cable is connected by using an Ethernet CAT5e cable as a substitute. Two twisted pairs are used to connect CAN_H and CAN_L (differential signals).
1-2. Development environment
The following tool setup is required. Please prepare the development machine requirements (OS, etc.) according to the requirements supported by the following tools.
- FPGA development tools (tested on the Windows version of Version 24.3.1)
- MCU Development Tool [IDE] (tested with Version 24.12 for Windows)
- MCU Development Tool [SDK] (Operation check was performed with SDK Version 24.12.00. Select "Processors > LPC -> LPC54000 > LPC546xx -> LPC54616J512" from the following page to generate and download the SDK).
- Terminal software (TeraTerm, PuTTY, etc...) TeraTerm is recommended since the TeraTerm macro (.ttl) is used to check the operation.)
Point: FPGA development tools are available with a free license for the Agilex™ 5 E-Series. Also, since the sample design includes Nios® V/m core, please obtain a free license for Nios® V. If you do not want to recompile, you can install only Quartus® Programmer.
How to obtain a Quartus® Prime Pro Edition free license file for Agilex™ 5 E development - (In Japanese)
How to obtain a license file for Nios® V Processor IP - (In Japanese) Point: The MCU development tools are available free of charge, although you must register as a user on the NXP site.
[NXP Microcontroller Beginner's Guide 0] How to install MCUXpresso IDE - (In Japanese)
[NXP Microcontroller Beginner's Guide 1] How to create a sample project in MCUXpresso IDE - (In Japanese)
2. Provided files
The table below lists the files required to run the samples introduced in this article, as well as the design files that can be provided.
Table 1. List of Provided Files
| File No. | File Name / Download Link | Summary | Update Date/Version |
| [1] |
lpcxpresso54616_freertos_generic-_for_sulfur_20240426_v1.11.zip |
MCU Software (MCUXpresso project) |
4/26/2024 v1.11 |
| [2] | FPGA design files (Quartus Prime project) |
1/29/2025 v1.8 |
|
| [3] |
sulfur_ghrd_top_hps_QP24.3.1_v1.8-_USE_MCUSPI.sof (sdmosc25MHz) sulfur_ghrd_top_hps_QP24.3.1_v1.8-_USE_MCUSPI.jic (sdmosc25MHz) sulfur_ghrd_top_hps_QP24.3.1_v1.8-_USE_MCUSPI_sdmosc125MHz.sof sulfur_ghrd_top_hps_QP24.3.1_v1.8-_USE_MCUSPI_sdmosc125MHz.jic |
FPGA Configuration Data files (.sof and .jic) |
1/29/2025 v1.8 |
| [4] | sulfur_can-if_test-20240417en.ttl | Macro for testing (for TeraTerm) | 4/27/2024 |
There are three files provided: MCU software, FPGA design (pre-built images and projects), and the verification macros. There are no changes to the Agilex™ 5 HPS (Hard Processor System) for this sample design.
Point: In addition to the files provided above, an SD card image for the HPS boot is required. Please obtain the Linux SD card image ( sdimage_agilex5_sulfur_QPDS24.3.1_v1.8.zip) from the following page
Note: Use the appropriate FPGA-related files [2], [3] according to the serial number of the SoM installed in the Sulfur Type-A. Different SDM OSC frequencies will not work properly.
Point: The SDM OSC clock frequency setting depends on the serial number of the SoM board. For SoM boards with serial numbers A5SOM1E024D0001 ~ A5SOM1E024D0025, the frequency is 125MHz; for other SoM boards, the frequency is 25MHz.
3. Running the Sample Design
This section describes how to run the sample designs using the pre-built images, and the MCU software can also be tested in the environment in which the Sulfur board was written at the time of shipping.
Please refer to Getting Started for basic instructions on how to use the Sulfur board, how to configure the FPGA, and how to write the SD card image.
Note: If you have rewritten the MCU software after acquiring the Sulfur board If you have already rewritten the MCU software after obtaining the Sulfur board, please follow the procedure described in 4-1, How to Open and Write MCU Projects to rewrite the software for this sample design.
3-1. Preliminary preparation/board setup
3-1-1. Cable Connection
With the power switch (SW18) in the OFF position, connect the cables as shown in Figure 2 and Figure 3.
In particular, although the MCU CN22 connector is a 10-pin GPIO header, only the following 3 pins are used. Check both pins of MCU-Link and Sulfur, and make sure to connect them correctly.
-
- Pin 2: GND
- Pin 3: UART_TXD
- Pin 4: UART_RXD
Figure 2. Board Setup 1 (Cable Connection)
Figure 3. Board Setup 2 (MCU Pin Header Connection Image)
3-1-2. DIPSW / Slide Switch Settings
The basic settings should be in accordance with the settings described in "4.2.2 DIPSW/Slide Switch Settings (Carrier Board) " and "4.2.3 DIPSW Settings (SoM)" in Getting Started.
The following is a description of the DIPSW / slide switch settings to be changed for this sample design.
-
- Set both CAN terminator switches ( SW 5 and 6 ) to ON (termination enabled)
- Set SW 4.2 on the back of the board to OFF (FPGA access Enable)
Note: SW4.2 can be implemented as a user switch on the MCU, but in the MCU sample software, it has the function of switching Enable/Disable access to the FPGA side, assuming that an FPGA design that does not include circuitry for the CAN interface is used.
3-1-3. Write & Install SD Card for HPS Boot
Download the Linux SD card image ( sdimage_agilex5_sulfur_QPDS24.3.1_v1.8.zip) and write it to the SD card. After the writing is complete, insert the SD card into the SD card slot on the Sulfur board.
Tip: Refer to "4.3 Creating an SD Boot Disk for Sulfur Type-A" in Getting Started for how to write the SD card image.
3-1-4. Writing FPGA Configuration File & MSEL Change (optional)
Point: If you do not want to rewrite the configuration ROM of the Sulfur board, skip this step. Use the .sof file to configure at runtime in a timely manner.
Select the appropriate .jic file from the 2. Provided files [3] to download and write. After writing is complete, change MSEL (SW1.1, 1.2, 1.3) to AS (Fast) mode (OFF, ON, ON).
Tip: Refer to "5.3.2 Writing .sof Files" in Getting Started for how to write the configuration file, and replace .sof to .jic in the file specified in Change File.
3-2. Design Execution/Operation Procedure
3-2-1. Power on the board
Switch the power switch ( SW18 ) to ON.
3-2-2. Setup of Terminal Software (TeraTerm)
Start the terminal software and set up the two serial terminal systems for FPGA and MCU.
For the COM port, select the terminal of FPGA and MCU referring to the following information.
-
- Connection name of FPGA: USB Serial Port (COMx)
- Connection name for MCU: MCU-Link VCom Port (COMx)
Figure 4 Terminal Software (TeraTerm) Setup
3-2-3. Checking MCU Terminal Display and MCU Software Version
The version information is displayed on the serial terminal of the MCU as shown in Figure 5.
Figure 5. Initial display of MCU terminal
If the version 1.11 and the time stamp before the Sulfur board was obtained are displayed, there is no problem. If the version information is different, rewrite the software for this sample design according to the procedure described in 4-1. How to open and write an MCU project.
Point: "FPGA is not ready, or SW4.2 is on." indicates that the FPGA configuration is not complete or SW4.2 status is not correct.
3-2-4. Writing FPGA Configuration File (.sof)
Point: This step is not necessary if 3-1-4. Writing FPGA Configuration File & MSEL Change (optional) has been executed.
Select the appropriate .sof file from [3] of the 2. Provided files to download and write.
Tip: Refer to "5.3.2 Writing .sof Files" in Getting Started for how to write the configuration file.
3-2-5. Confirm FPGA (HPS) Terminal and Start U-Boot Prompt
The HPS boot log will start to be displayed on the serial terminal for FPGA as soon as the FPGA configuration is completed. The display of "Hit any key to stop autoboot:" will be followed by a 5-second countdown. Enter the Enter key before 5 seconds have elapsed to enter the U-Boot prompt state.
Figure 6. Initial display of HPS terminal and start of U-Boot prompt
Point: If no key input is detected in time, Linux will start booting. In that case, write the .sof file again. If you use a .jic file, press the FPGA_RST button (SW11) or turn the power on again.
3-2-6. Checking the interface between FPGA and MCU
If you are using a .sof file, press the MCU reset switch (MCU SW7).
Confirm that "@@ Self Check for SPI I/F: result = SUCCEEDED." is displayed on the serial terminal on the MCU side.
Figure 7. Self-check of the interface between FPGA and MCU
Point: If the result of Self Check for SPI I/F is "FAILED", you may have the wrong FPGA configuration file. Review the .sof/.jic file and configure the FPGA again.
3-2-7. Start CAN Communication Test
Execute the test macro ([4] in 2. Provided File ) from the terminal for the FPGA.
This macro does the following. Open [4] for more details.
-
- HPS-to-FPGA bridge open
- Stores the transmitted data in the CAN0 data FIFO
- Stores the transmitted data in the CAN1 data FIFO
- Stores instructions to CAN1 in the transmit event FIFO
- Waiting for CAN1 TX → CAN0 RX to be folded back
- Confirmation of data returned from CAN1 TX to CAN0 RX
- Stores the instruction to CAN0 in the send event FIFO
- CAN0 TX → Wait for return to CAN1 RX
- Confirmation of data returned to CAN0 TX → CAN1 RX
- Display of data verification result "-- Test Succeeded! --" or "XXXX Test Failed XXXX".
3-2-8. CAN Communication Test Execution & Result Confirmation
After the test macro execution starts, CAN communication loopback is performed from FPGA to MCU via MCU in the order of CAN1 -> CAN0 and CAN0 -> CAN1. The result of the received data verification is also displayed in a pop-up window.
Figure 8. Execution image of CAN communication test
This is the end of the sample design execution procedure.
4. Explanation of the sample design and supplementary information
From here, we will introduce various information that may be necessary in addition to the execution of the sample design.
4-1. How to open and write an MCU project
This section introduces the procedures for building, debugging, and writing ROM to MCU software.
This explanation assumes that the MCUXpresso IDE and SDK have been installed.
4-1-1. Starting MCUXpresso
Launch "MCUXpresso IDE v24.12.148" from the Windows Start menu.
Following the splash window, a dialog box for specifying a workspace will appear.
Figure 9. Launching the MCUXpresso IDE
4-1-2. Importing MCU Project
After the MCUXpresso IDE is launched, import the project file ([1] in 2. Provided Files ) by referring to Figure 10.
Tip: In addition to the menu shown in Figure 10, you can also launch the import screen from the File menu -> Import.
Figure 10. Importing an MCUXpresso project
The following warning window may appear when executing project import. This warning message is displayed when the SDK version used when the project was created is different from the import destination SDK version.
Figure 11. Warning message after import is complete
Note: The sample project was created with SDK Version 2.14.0. However, the sample project has been tested with SDK Version 24.12.00 too. If you use a further newer SDK version, please be aware that problems may occur.
4-1-3. Writing a Pre-built Image
A pre-built executable file (axf image) and Debug Configuration settings are included in the MCU project.
By starting Run menu -> Debug Configuration and selecting the configured Debug Configuraion, you can write the same program to the boot flash of the MCU as when shipped from Sulfur. Referring to Figure 12, select the Program tab of the GUI Flash Tool and click the Run... button. Click the "Run..." button after selecting the "Program" tab of the GUI Flash Tool.
Figure 12. Writing the pre-built image
Click OK button and close the Debug Configuration window to finish the operation.
Figure 13. Pre-built image is written successfully.
4-1-4. Other Operations (Build, Debug, etc.)
Other operations can be handled in the same way as in a general Eclipse-based IDE environment.
Debugger connection settings can be made directly from the Debug Configuration included in the project; simply open the Debug Configuration and press the Debug button to start debugging.
For more information, please refer to the tool documentation.
References: MCUXpresso IDE for NXP MCUs | Linux, Windows and MacOS | NXP Semiconductors
Reference material: NXP Microcontroller Beginner's Guide Summary Site - Semiconductor Business - Macnica - (In Japanese)
4-2. FPGA to MCU Interface
This section describes the mechanism for passing data between the FPGA and the MCU implemented in this sample design.
4-2-1. FPGA Circuit Block & MCU Task Configuration
Figure 14 shows the internal structure of the FPGA side.
The FPGA and MCU are connected by an SPI bus, and the MCU (SPI master) provides read/write access to the FPGA via the SPI Slave to Avalon-MM Bridge. 5 types of FIFOs are implemented for data transfer to and from the 2 CAN interfaces. The following five types of FIFOs are implemented to pass transmit/receive data to the two CAN interfaces.
-
- CAN send data: The MCU periodically monitors the FIFO and processes the send request from the FPGA.
- CAN receive data: All data received by the MCU is stored in the FIFO on the FPGA side.
Note: Both the MCU and FPGA must monitor the FIFO periodically to prevent FIFO Full.
Tip: The supported CAN communication specifications are based on the specifications of the CAN controller built into the MCU.
Figure 14. FPGA-MCU Interface (FPGA internal block)
The MCU software implementation uses FreeRTOS to process one interface with the FPGA side and two CAN interfaces in parallel. The task configuration and the interface between tasks are outlined in Figure 15. For details, please refer to the source code.
Figure 15. Interface between FPGA and MCU (MCU internal tasks)
4-3. FPGA Internal FIFO Specifications
The following five systems of FIFOs are provided.
-
- Transmit event FIFO (x1): Used for transmit event notification including CAN 0 and 1 selection, data size, and various parameters.
- Transmit data FIFO (x2): Used to pass and receive data (payload) to be placed in a CAN frame. Agilex 5 loads data in the amount corresponding to the data size to be included in the transmit event.
- Receive frame FIFOs (x2): Used to pass all the information (both parameters and payload) of the received CAN frame; the MCU loads all the information received from the CAN controller.
The addresses of the FIFOs inside the FPGA are set as follows.
In the figure, the blue connection is for access from inside the FPGA (HPS or Nios V) and the orange connection is for access from the MCU via SPI.
Figure 16. Bus Connection to FIFO for CAN I/F and Base Address
When accessing from the MCU, the value of Base in Figure 16 is used as the address value to be specified when accessing via SPI.
When accessing from the HPS (lwhps2fpga), access the base address 0x00_2000_0000 of lwhps2fpga plus the base address 0x0000_2000 of the subsystem implementing the FIFO (subsys_canif_0), and add the address value displayed in Base in Figure 16. Access is performed at the address obtained by adding the address value displayed in Base in Figure 16.
The following is the setting screen including the base address of the subsystem (subsys_camof_0).
Note: Although not used in the sample, it is connected to the bus so that it can be accessed from Nios V.
Figure 17. Bus Connection to CAN I/F Subsystem and Base Address
4-3-1. Data Structure of Transmission Event FIFO (1 fifo: for both CAN 0 and 1)
Since it is necessary to have CAN 0 and 1 identification information, it is implemented in an original format.
-
- The information elements to be stored in the FIFO are the payload of the event FIFO on the MCU side, the payload of the CAN controller FIFO on the MCU side, and the payload of the event FIFO on the MCU side.
- For both the event FIFO and buffer FIFO on the MCU side
Below are reproduced the specifications of the Tx buffer (FIFO) and Tx event (FIFO) of the CAN controller of the MCU. The original format is defined with contents that can handle the information contained in T0, T1, E0, and E1 in the figure.
Figure 18. Transmission FIFO Specifications for the MCU CAN Controller (taken from the NXP MCU manual)
Figure 19. Transmission Event FIFO Data Structure (Original Format)
4-3-2. Data Structure of Transmit Data FIFO (2 fifos: CAN 0, 1 independent)
The data specifications of the FIFO for transmit data are the same as the DB field of the CAN controller FIFO on the MCU side. The data structure shown in Fig 134, T2 to Tn of the Tx buffer element in Figure 18 is stored as is.
4-3-3. Data Structure of Receive Frame FIFO (2 fifos: CAN 0, 1 independent)
The data specifications of the FIFO for receive frame are the same as those of the CAN controller FIFO on the MCU side. The same data structure as in the following specification is stored in the FIFO as it is.
Figure 20. MCU CAN controller FIFO specifications for reception (taken from the NXP MCU manual)
4-4. SPI-to-AVMM Bridge Driver
To access the FPGA from the MCU via SPI, a dedicated driver must be implemented.
The sample driver published in the following page is used as a base, modified to use the API for the SPI controller of NXP MCUs.
Reference: SPI Agent to Avalon Host Bridge Design Example | Intel
The source/alt_spi_to_avalon_bridge folder of the MCU software project contains the complete source code for the modified driver for NXP MCUs. For more detailed information, please refer to the source code directly.
Conclusion
We have introduced the procedure to check the CAN I/F communication by combining the FPGA and MCU on the Sulfur board.
Although the Sulfur board is equipped with an MCU for the purpose of implementing CAN I/F, it can be used for other applications and verifications by customizing the software for the MCU.
Various information on how to use the MCU is available on the following page. We hope you will find it useful.
Reference material: NXP Microcontroller Beginner's Guide Summary Site - Semiconductor Business - Macnica - (In Japanese)