New Engineer's Blushing Blog

• External Memory Interface ~ ALTMEMPHY? UniPHY? ~
• External Memory Interface - Read ? Write ?
• Memory IP ~ accurate and efficient data transfer
• PLL Loop Bandwidth and Spread Spectrum
• Thanks to line buffers - Kuramii's struggles with C Language
• Intel® FPGA Configuration Sequence
• Why should I pay attention to Jitter?
• External Memory Interface - What is PHY? -
• Difference between VHDL and Verilog HDL - Signals with different bit widths -
• Rescue the Lost Pins! FPGA Pin Assignments Part 2
• Relationship between Quartus and Board Simulation - Derivation of IBIS file (1)
• Relationship between Quartus and Board Simulation - Derivation of IBIS File (2)
• Test bench allergy resolution
• Useful to know! Programming Options!
• A little story about the I/O Standard - Tools follow the device
• Note the Aamplitude of LVDS
• Difference between synchronous and asynchronous circuits - Comparison -
• Sequential processing and parallel processing
• Difference between synchronous and asynchronous circuits - Conclusion -
• EPCS and EPCQ ～Precautions for use
• Logic Synthesis and Place and Route
• SDR and DDR - Processing DDR data with FPGA
• About clock signal accuracy notation
• FPGA I/O Functions - What is Voltage Conversion? -
• Frequency Get with Frequency Division !
• Masuo's FPGA Board Fabrication #2 : Damping Resistors and Overshoots
• PLL Applications (Reduce EMI by Spread Spectrum!)
• About Jitter
• configuration time
• Types of logic circuits - Sequential？ Combinational？