New Engineer's Blushing Blog

• Oscilloscope Trigger - Triggering?-
• About Crystal Resonator
• Frequency Accuracy of Clock Generators
• Inside the FPGA: The Curious Relationship with DSPs
• [Nios II] Booting from on-chip memory - Qsys modification
• FPGA I/O Functions - Programmable Current strength - Part 1
• What is configuration mode?
• Rescue the Lost Pins! FPGA Pin Assignments Part 1
• Unused pin rhapsody - Part 2
• The CPU is a capable performer
• The reality of ASCII codes [Part 3] - Subtract '0' from num ? -
• Microcontroller watchdog? Watchdog Timer
• What is the role of MMU? - Part 2
• PLL IP Usage Notes - Pitfalls of Convenience
• The reality of ASCII codes [Part 1] - 1 but 49 ? Input/output format -
• Divider of Clock
• FPGA I/O Function - Voltage Conversion with Open Drain! -
• The reality of ASCII codes [Part 2] - Correspondence between ASCII codes and characters
• NULL, what the heck is it? ~ indicating the end of a string ~
• I was in trouble because I didn't know! A beginner's attempt to build a 7seg clock using an FPGA evaluation kit #3 - Software Design
• Compare the uses of RTL Viewer and Technology Map Viewer
• What is the role of MMU?
• FPGA I/O Functions - Programmable Current strength - Part 2
• Pin Assignment - What pin is this signal on?
• Pin Assignment in Quartus Prime ～ For those who like text-based
• Can't people read? The Mystery of Binary Files
• What is UART? - The Difference Between Serial and Parallel Communication -
• The Magic of Coils ~Boosting Voltage~
• Programming? Configuration?
• Selection of Configuration ROM