SoC
- U-Boot Environment Variable Settings and Notes
- How to handle SD card images in WIC format
- Overview of Linux boot options file (extlinux.conf)
- Rewrite U-Boot on SD card for boot in Windows environment (SoC EDS v20.1~)
- Workaround for bsp-create-settings execution error in SoC EDS environment
- Configure new U-Boot handoffs and device trees
- Workaround for sopc-create-header-files execution error in SoC EDS environment
- Supplement to Cygwin Setup for SoC EDS
- How to starting up the second core in a dual-core processor (Cyclone® V SoC / Arria® V SoC)
- Notes on notifying multicore of interrupts
- IRQ port and interrupt pending register used for interrupts from FPGA to HPS
- FPGA-to-SDRAM interface opening configuration for SoC FPGAs (U-Boot 2019.04)
- How to start U-Boot (v2019.04 or later) with Arm® DS (DS-5) Debugger (Cyclone® V SoC / Arria® V SoC edition)
- How to start U-Boot (v2019.04 or later) with Arm® DS (DS-5) Debugger (Arria® 10 SoC edition)
- HPS Pin Location and Assignment Notes for SoC FPGAs
- SDRAM area address mapping setting status before and after SoC FPGA boot
- How to use ECC Error Injection
- Calibration results to be checked in case of QSPI inaccessibility
- U-Boot HPS-FPGA Bridge Open Command for SoC FPGAs
- Bootloader generation flow for SoC EDS v19.1 Std / v19.3 Pro or later (Arria® 10 SoC edition)
- How to issue a reset signal from the HPS to the FPGA (Arria® 10)
- Bootloader generation flow for SoC EDS v19.1 std / v19.3 pro or later (Appendix: Building Linux binaries - Cyclone® V SoC / Arria® 10 SoC edition)
- Bootloader generation flow for SoC EDS v19.1 std / v19.3 pro or later (Cyclone® V SoC / Arria® V SoC edition)
- How to issue a reset signal from the HPS to the FPGA (Cyclone® V / Arria® V)
- How to add HWLib by Makefile
- How to perform read/write test to memory/registers in U-Boot
- Building Preloader / U-Boot with WSL [Part 2: Build]
- Semi-Hosting for SoC FPGAs
- How to Edit U-Boot Scripts
- How to create SD card image for SoC FPGA boot