In this column, we introduce "FPGA technical information that is not well-known unexpectedly, but what you know makes a difference.
The contents are useful for a wide range of people from FPGA beginners to veterans, so please stay with us to the end.
Part 10: How to Reduce DC Power and Leakage Power
Let's examine how to reduce DC current (Idc) and leakage current (Ileak), which are one of the leakage power parameters in the power consumption calculation formula.
Methods to reduce ldc
(a) Maintaining a logical state in which no DC power flows
As described in the third column, keep the logic state where no DC current flows in the pull-up/down buffer for a long time.
(b) Avoid signal conflicts
When signals in a bi-directional buffer conflict (L and H signals collide), Vcc and GND are connected, which consumes a considerable amount of power.
Avoid conflicts or keep the conflict time short.
(c) Increase the pull-up/down buffer resistance
Increasing the resistor value will cause the waveform to be flattened, but the current through the resistor will be reduced.
(d) Use of power-down mode
For blocks that support power-down mode, frequently put them in power-down mode when operation is not required.
Methods to Reduce lleak
The most effective ways to reduce leakage are by increasing Vt (threshold voltage) and power gating.
Intel supports both of these low-power techniques.
(a) Raising Vt (threshold voltage)
Vt (threshold voltage) is the dividing line between low and high logic.
For example, increasing the threshold height reduces leakage current because it is more difficult for a charge to overcome the threshold, but it also makes it more difficult for a normal operating charge to overcome the threshold, so the speed is reduced.
Thus, increasing Vt lowers leakage current very much, but has the disadvantage of slowing down. It is similar to hurdle running.
With Intel's Programmable Power Technology, Quartus®Prime automatically lowers Vt in the critical path for higher speed and increases Vt in the rest of the circuit for lower power.
This is a highly effective technique because there are few critical paths in the entire circuit.
In the future, when the timing accuracy of Quartus Prime becomes more accurate, the Vt increase range becomes larger, and Vt can be controlled dynamically, it will be even more effective, making it a promising low-power technology for the future.
Please note that this is a technology that mainly reduces leakage power, although competing FPGA vendors evaluate this programmable power technology only in terms of dynamic power and call it ineffective.
(b) Power gating
Power gating is a function that cuts power to circuits that are not in use.
Intel has begun to support power gating in DSPs and memory cells.
If dynamic power gating of logic parts becomes possible in the future, leakage power can be significantly reduced, making this a promising low-power technology.
(c) Small chip area
There are two ways to reduce chip area: by reducing the size of the circuitry and by using a miniaturized process.
Although the leakage power of miniaturized FPGAs is higher, the chip area is smaller because the circuit size is larger.
Power consumption increases with the latest process FPGAs because of the increased circuit size and higher speed.
Power consumption values announced by FPGA vendors are compared using the same circuit size and speed, so power consumption appears lower.
(d) Partial Reconfiguration
Partial reconfiguration is a function that changes the circuit configuration of some blocks during operation.
Unused circuits are eliminated, thus reducing the leakage power for those circuits.
(e) Temperature reduction
The subthreshold leakage current, which is currently a problem, is highly temperature-dependent and is said to increase 10-fold when the temperature rises by 50°C. The temperature of a circuit can be reduced by lowering the dynamic power or by using a cooling method.
Lowering the chip temperature by reducing dynamic power or considering cooling methods and board layout can lower leakage power.
Although Siemens EDA's HyperLynx Thermal cannot perform exact board thermal analysis, it is recommended because it is inexpensive and anyone can easily disperse FPGA heat generation.
(f) Lower Vcc
This method was introduced in Part 7, but since Vcc is lowered, leakage power is also lowered.
- SmartVID
"SmartVID" lowers Vcc, thus reducing leakage power.
- VCC PowerManager
"VCC PowerManager" lowers Vcc, thus reducing leakage power.
(g) Low static power device grade
Intel offers a "low static power device grade" FPGA that consumes less static power than standard power devices while maintaining performance.
Leakage power can be reduced simply by adopting this device.
Knowing the Difference! FPGAs: The Only Thing You Need to Know Series
Power Consumption
- Part 1: Three Tips for Low Power Consumption
- Part 2: Is Clock Gating (Gated Clock) Effective?
- Part 3: Is this leakage power? No, it is DC power.
- Part 4: Why Precision Power Simulators Were Never Used
- Part 5: Is this the ultimate low-power method?
- Part 6: How to Reduce Load Capacitance (C)
- Part 7: How to Reduce Signal Amplitude (Vs) and Supply Voltage (VCC)
- Part 8: How to reduce the operating frequency (F) and toggle ratio (N).
- Part 9: How to Reduce Short-Circuit Power
- Part 10: How to reduce DC power and leakage power
Verification
- Part 1: What is the first thing to ask designers who are concerned about design quality?
- Part 2: Verification methods not recommended for designs that have already been commercialized.
- Part 3: Verification is a combination of various methods.
- Part 4: FPGAs have more defects than ASICs - Asynchronous clocks.
- Part 5: What is formal verification?