FPGAs: The Only Thing You Need to Know About Them - Power Consumption [Part 5] Is This the Ultimate Low Power Consumption Technique? – Macnica Altera FPGA Insights

In this column, we introduce "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for a wide range of people from FPGA beginners to experienced users, so please stay with us to the end.

Part 5: Is This the Ultimate Low-Power Design Technique?

Low-power design techniques are a series of detailed measures.
Rather than memorizing detailed measures, it is important to understand power consumption calculation formulas and parameters used in them, and to design with power consumption in mind on a regular basis.

Even if you have been thinking that it is troublesome to understand the calculation formulas, we recommend that you take the time to look at them carefully at least once.
Seeing which parameters are affected by the low-power methods you know will speed up your understanding.

1.1 Power Consumption Formula for CMOS Circuits

Power consumption = Dynamic power + Leakage power
= [Switching power + Short circuit power] + Leakage power
= [0.5*(C*Vs*VCC*F)*N] + [Q*VCC*F*N] + [(Idc+Ileak)*VCC]

C: Load capacitance
Vs: Signal amplitude
VCC: Supply voltage
F: Operating frequency
N: Signal transition frequency (toggle rate)
Q: Charge due to through-current
Idc: Circuit specific DC current
Ileak: Leakage current

1.1.1 Dynamic power

This is the power when a signal transitions, and is the sum of switching power and short-circuit (through-circuit) power.

(1) Switching power

This is the power consumed when a cell operates and charges or discharges the load capacitance.
The load capacity is the sum of the wiring capacity and the input pin capacity of the next cell.

For example, when "L" is input to the input of an inverter, the pMOS turns "ON" and the nMOS turns "OFF", and current flows from VCC to the inverter. The current flows from VCC and charges the capacitance of the wiring and the input pins of the next stage. At this time, power is consumed by the pMOS resistance.

Next, when the inverter input is set "H", pMOS turns "OFF" and nMOS turns "ON", and the charge charged in the load capacitance flows through nMOS to GND. The charge charged in the load capacitance flows through nMOS to GND. At this time, power is consumed by the nMOS resistance.
This capacitance is the sum of the wiring resistance and the input pin capacitance of the next-stage cell. The longer the wiring and the larger the Fanout, the more switching power is consumed.

Figure 1 CMOS inverter circuit and switching power

(2) Short Circuit Power

In CMOS, when the input signal is stable at "L" or "H", either pMOS or nMOS is always turned off and no current flows from VCC to GND except leakage current.
CMOS is said to have low This is why CMOS is said to have low power consumption. However, if the rise or fall of the input signal is slow, both pMOS and nMOS will temporarily be slightly open.
At this time, a short-circuit current flows from VCC to GND, and this power is called short-circuit power.

1.1.2 Leakage Power

Leakage power is the power that is passed by the following four types of leakage currents.
In older processes, leakage power was negligibly small, but in the latest processes, leakage power is considerably larger.
These leakage powers are consumed regardless of operation as long as voltage is applied to the transistor.
Today, subthreshold leakage currents and gate leakage currents are the majority.
Subthreshold leakage currents are highly temperature dependent, so higher temperatures further increase leakage power.

Category	Description	Cause	Temperature dependence
Sub-threshold leakage current	The current that flows between the source and drain when the transistor is off	Vt drop of transistor	High
Gate leakage current	Current flows from the gate through the gate oxide to the source due to the tunnel effect.	Thinner gate oxide	Low
Junction leakage current	Current flowing between the source, drain and substrate	Increased concentration of impurities and crystal defects in elements	Low
Gate-Induced Drain Leakage Current	Current due to electrolysis between the gate and drain	Thinner gate oxide	Low

Table 1. Comparison of various leakage currents

Figure 2. nMOS transistor structure and leakage current

From the next issue, we will introduce specific methods to reduce each parameter.

FPGA: The Difference Between Here and There Series

Power Consumption

Verification

FPGAs: The Only Thing You Need to Know About Them - Power Consumption [Part 5] Is This the Ultimate Low Power Consumption Technique?