FPGA: The Only Thing You Need to Know - Power Consumption [Part 6] How to Reduce Load Capacity (C) – Macnica Altera FPGA Insights

In this column, we introduce "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for a wide range of people, from FPGA beginners to veterans, so please stay with us until the end.

Part 6: How to Reduce Load Capacitance (C)

Low-power design techniques are a series of detailed measures.

In order to understand the power consumption calculation formula, we will introduce some typical low-power methods.

First, we will examine how to reduce load capacity "C" in the power consumption formula.

Generally, the load capacitance "C" is the sum of the "wiring capacitance" and the "pin capacitance of the input pins connected to the next stage.
Reducing "C" not only reduces dynamic power, but also reduces leakage power because fewer resources are required.

To make the image easier to understand, let's compare the load capacitance to a bucket and the charge to water.
There are two ways to fill all buckets with less water: by "reducing" the number of buckets or by "reducing" the size of the buckets.

　　Figure 1: CMOS circuit in operation

First, let's consider how to reduce the number of buckets, i.e., how to reduce FPGA resources.

Reduce the parallelism by increasing the speed.

Running a circuit at 500 MHz at 1 GHz halves the data path width and significantly reduces resources.
For example, Stratix® 10, with its HyperFlex architecture, delivers twice the performance of previous models, so you can cut the parallelism of the circuit in half and save resources.

Reducing ALM Utilization

The basic module of an FPGA, the ALM (Adaptive Logic Module), consists of two ALUs for combinational circuits, adders, registers, and so on. For the same logic, the "C" can be reduced by reducing the number of ALMs used.

(a) Synthesizing with "area priority" in Quartus® Prime Pro reduces ALU utilization.

　　Table 1: Difference in ALU usage between area priority and speed priority

　　Table 2: Power consumption reduction ratio in Table 1

Since the maximum fanout value is fixed for FPGAs, multiple ALMs may be used when speed is increased.
Blocks that do not require high speed should be synthesized with "area priority".

(b) Hard Macro

Although it is possible to create memory and DSP with ALMs for logic, hard macros for memory and DSP are optimized for the size and number of transistors, so "C" is much smaller.
As much as possible, use dedicated hard macros for memory or DSP instead of ALMs.

(c) Power-Driven Synthesis

If you use the logic synthesis option and make the area extremely small, the number of toggles increases, which may conversely increase power consumption.
Quartus Prime's "Power-Driven Synthesis" gives priority to low-power consumption for logic synthesis.

(d) Partial Reconfiguration

Partial Reconfiguration is a function that changes the circuit configuration of some blocks during operation.
Removing unused circuits avoids wasting power due to leakage power and clocks of those circuits.

(e) Reducing the number of ALMs by optimizing architecture and algorithms

Be aware that the circuit size should be reduced when designing algorithms.
Measures taken during algorithm design are more effective than detailed low-power measures taken after RTL is completed.

(f) Adopt FPGA with high speed (small speed grade)

Logic synthesis on a fast FPGA may generate smaller circuits than on a slow FPGA.
Logic synthesis with unreasonable performance requirements may synthesize circuits with increased parallelism, so it may be optimal to select a device with one higher speed grade than a device with one larger area.

(g) Optimization of HDL description

Depending on how HDL is written, fewer resources are used.
For example, in Verilog-HDL, fewer "always" means fewer registers, and more "don't-care (indefinite)" means fewer resources.
There are numerous other ways to optimize area by description.

 module dff(DATA, CLK, Q, QN); 
 input DATA, CLK; 
 output Q, QN; 
 reg Reserve, Q, QN; 

 always @(posedge CLK) 
 begin 
 Reserve <= DATA; 
 end 
 always @(Reserve) 
 begin 
 Q <= Reserve; 
 QN <= ~Reserve; 
 end 
endmodule

Description 1: Description with many registers

 module dff(DATA, CLK, Q, QN); 
 input DATA, CLK; 
 outputQ, QN; 
    reg Q, QN;

    always @(posedge CLK) 
        begin 
 Q <= DATA; 
 QN <= ~DATA; 
 end 
 endmodule

Description 2: Description with few registers

(h) Code Coverage

Code coverage can be used to find unused circuits.
Since there are cases where circuits that are no longer needed are left behind when there are many specification changes, use code coverage to search for and delete unnecessary circuits.

The next method is to reduce the size of the bucket, or capacity.

Reducing Capacity

(a) Shorten nets with high toggle ratio

Since the wiring portion of the FPGA consumes a large amount of power, nets with a high toggle ratio should be wired as short as possible.

Nets with high toggle rates between ALMs can be connected between ALMs in the logic array block (LAB) to reduce wiring capacity.
For example, shared control signals such as enable and set are difficult to fit in the LAB if they are shared by many circuits, so control signals should be as few as possible.

That said, it is difficult to do manually.
Quartus Prime's "Power-Driven Fitting" can be used to reduce wiring length by prioritizing nets with many toggles, and to split memory to reduce power consumption. For best results, please input "as accurate toggle information as possible".

Partitioning the wirings with many toggles so that they are inside the block is also effective.

(b) Shorten the wiring around the FPGA

Shortening the wiring length connected to the FPGA output pins will reduce the power consumption of the output buffer.
The external load capacitance is an order of magnitude larger than the internal wiring capacitance, so the effect is significant.

Since FPGAs have a high degree of freedom in pin placement, assign pins so that the wiring becomes shorter, taking into account the location of devices around the FPGA.

(c) FPGA to 1 chip

By incorporating the functions of older process devices around the FPGA into the FPGA, the wiring capacity and devices around the FPGA can be reduced. In particular, analog portions should be digitized as much as possible.
Since the FPGA process is finer and consumes less power than the peripheral devices, power consumption may be lower than that realized by the older process devices.

Recently, if the microcontroller around the FPGA is contained in one device with an Intel SoC FPGA, the wiring capacity between the FPGA and the microcontroller can be reduced, resulting in higher speed and lower power consumption.
For high-speed communication, it is recommended to use a transceiver built into the FPGA instead of placing SerDes outside the FPGA.

(d) Utilize Logic Lock

When using Logic Lock block-based designs, partition the blocks to reduce the number of toggles between blocks, since the routing between blocks is often longer than within blocks.

(e) Adoption of fine process devices

A finer process has smaller transistors and therefore smaller capacitance.
If the circuit size is the same, using devices with the latest miniaturized process will consume less power.

Reduction of Pin Capacitance

Non-Intel FPGAs and ASICs may use tri-state buffers on the bus.

Tri-state buffers have very large input pin capacitance when closed, so it is recommended to use a multiplexer (selector) instead of a tri-state buffer on the bus.

　　Figure 2: Example of using a tri-state buffer on the bus

There are many other ways to reduce "C."
Try to reduce the number of transistors used and shorten the wiring as much as possible.

FPGA: The Difference Between the Best and the Worst Series

Power Consumption

Verification

FPGA: The Only Thing You Need to Know - Power Consumption [Part 6] How to Reduce Load Capacity (C)