FPGA Knowledge Base -Power Consumption- [Part 7] How to Reduce Signal Amplitude (Vs) and Supply Voltage (VCC)

This column introduces "FPGA technical information that is surprisingly little known but makes a difference if you know it.
The contents are useful for everyone from FPGA beginners to experienced users, so please stay with us until the end.

Part 7: Reducing Signal Amplitude (Vs) and Supply Voltage (VCC)

This section discusses how to reduce the voltage Vs and VCC from the power consumption calculation formulas.

Since Vs=VCC for the core voltage in general, "Vs (signal amplitude) * VCC (supply voltage)" in the calculation formula can be expressed as "V2.
Switching power is not only proportional to the square of the supply voltage, but also greatly affects short-circuit power and leakage power.

Core Voltage (VCC) Reduction

Core voltage has a very large impact on power consumption, but it is difficult for designers to change core voltage.
However, Intel offers many options to reduce core voltage, and we encourage you to take advantage of them.

(a) SmartVID

SmartVID is a way to reduce power consumption while still operating at spec speed.

Due to manufacturing variations, some devices run faster and some run slower than others, even with the same FPGA.
Intel writes the minimum voltage at which the device can sustain operation into the device during outgoing testing.
This value is called the "SmartVID."

For example, an FPGA with a base of 0.9V and a SmartVID of 0.8V will operate at (0.8/0.9)2, or 20% lower switching power. In addition, lowering the voltage also reduces leakage power (up to 40% reduction for Arria® 10).

(b) VCC PowerManager

VCC PowerManager is a way to reduce power consumption at a slower speed.
Since there is a margin of speed in high-speed speed grade devices, power consumption can be lowered by deliberately reducing the speed (i.e., lowering the voltage).

For example, if performance priority is given, use 0.95V, and if power priority is given, run the device at 0.9V, although the speed grade is reduced by one or two steps. Of course. Either voltage can be used to verify timing with Quartus® Prime.

A way to compensate for the slower speed is parallelization and pipelining.
Incidentally, in ASICs, Stratix® 10 has doubled its speed by pipelining, so VCC PowerManager is an effective method.

　　Figure 1: Example of lowering the voltage to compensate for the increase in speed due to parallelization

　　Figure 2: Example of lowering the voltage to compensate for the increase in speed due to pipelining

(c) Power Gating

Clock gating is a method of "stopping the clock" of a block only when it is not in use.
Power gating is a method of "stopping the power supply" only when it is not in use.

See [Part 8] for more information on clock gating.
Intel has begun to support power gating in DSPs, memory cells, etc.

(d) Programmable Power Technology

When compiling a design in Quartus Prime, if there is a timing margin, put it in low-power mode with an increased threshold. This has a significant impact on leakage power and also affects dynamic power since the threshold is changed.

(e) Low-voltage devices

There is a family of Intel FPGAs that offer low voltage in addition to the normal voltage.
These FPGAs can be used for low-voltage operation.

(f) Latest Process Devices

The newer the process, the lower the core voltage, so simply switching to the latest FPGA will lower the core voltage.
However, a circuit that operates slowly will have a higher percentage of leakage power than dynamic power, so the total power consumption may be lower with the older process.

Signal Amplitude (Vs) Reduction

(a) Small-signal-amplitude I/O

Using small-signal-amplitude I/O lowers power consumption.
Small-signal-amplitude I/O is not only low-power but also high-speed, so it is an I/O that should be used aggressively.

Intel offers many options to reduce the voltage.

Know the difference!

Power Consumption

Verification